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2f3956c41c
When switched to the MI scheduler for P9, the hardware is modeled as out of order. However, inside the MI Scheduler algorithm, we still use the in-order scheduling model as the MicroOpBufferSize isn't set. The MI scheduler take it as the hw cannot buffer the op. So, only when all the available instructions issued, the pending instruction could be scheduled. That is not true for our P9 hw in fact. This patch is trying to enable the Out-of-Order scheduling model. The buffer size 44 is picked from the P9 hw spec, and the perf test indicate that, its value won't hurt the cpu2017. With this patch, there are 3 specs improved over 3% and 1 spec deg over 3%. The detail is as follows: x264_r: +6.95% cactuBSSN_r: +6.94% lbm_r: +4.11% xz_r: -3.85% And the GEOMEAN for all the C/C++ spec in spec2017 is about 0.18% improved. Reviewer: Nemanjai Differential Revision: https://reviews.llvm.org/D55810 llvm-svn: 350285
54 lines
1.9 KiB
LLVM
54 lines
1.9 KiB
LLVM
; RUN: llc -verify-machineinstrs -mcpu=pwr9 -mtriple=powerpc64-unknown-linux-gnu < %s | FileCheck %s
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; RUN: llc -verify-machineinstrs -mcpu=pwr9 -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck %s
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; RUN: llc -verify-machineinstrs -mcpu=pwr8 -mtriple=powerpc64-unknown-linux-gnu < %s | FileCheck %s \
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; RUN: --check-prefix=CHECK-ITIN
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; RUN: llc -verify-machineinstrs -mcpu=pwr8 -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck %s \
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; RUN: --check-prefix=CHECK-ITIN
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; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mtriple=powerpc64-unknown-linux-gnu < %s | FileCheck %s \
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; RUN: --check-prefix=CHECK-ITIN
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define void @bn_mul_comba8(i64* nocapture %r, i64* nocapture readonly %a, i64* nocapture readonly %b) {
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; CHECK-LABEL: bn_mul_comba8:
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; CHECK: mulhdu
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; CHECK-NEXT: mulld
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; CHECK: mulhdu
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; CHECK: mulld
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; CHECK-NEXT: mulhdu
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; CHECK-ITIN-LABEL: bn_mul_comba8:
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; CHECK-ITIN: mulhdu
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; CHECK-ITIN-NEXT: mulld
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; CHECK-ITIN-NEXT: mulhdu
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; CHECK-ITIN-NEXT: mulld
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; CHECK-ITIN-NEXT: mulhdu
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%1 = load i64, i64* %a, align 8
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%conv = zext i64 %1 to i128
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%2 = load i64, i64* %b, align 8
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%conv2 = zext i64 %2 to i128
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%mul = mul nuw i128 %conv2, %conv
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%shr = lshr i128 %mul, 64
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%agep = getelementptr inbounds i64, i64* %a, i64 1
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%3 = load i64, i64* %agep, align 8
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%conv14 = zext i64 %3 to i128
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%mul15 = mul nuw i128 %conv14, %conv
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%add17 = add i128 %mul15, %shr
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%shr19 = lshr i128 %add17, 64
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%conv20 = trunc i128 %shr19 to i64
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%bgep = getelementptr inbounds i64, i64* %b, i64 1
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%4 = load i64, i64* %bgep, align 8
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%conv28 = zext i64 %4 to i128
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%mul31 = mul nuw i128 %conv28, %conv2
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%conv32 = and i128 %add17, 18446744073709551615
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%add33 = add i128 %conv32, %mul31
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%shr35 = lshr i128 %add33, 64
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%conv36 = trunc i128 %shr35 to i64
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%add37 = add i64 %conv36, %conv20
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%cmp38 = icmp ult i64 %add37, %conv36
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%conv148 = zext i1 %cmp38 to i64
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store i64 %conv148, i64* %r, align 8
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ret void
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}
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