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3cb5f18fb0
Add POPCNT, LZCNT, TZCNT to the list of instructions that have false dependency. Add a test to make sure BreakFalseDeps breaks the dependencies for these instructions. Update affected tests. This fixes bugzilla https://bugs.llvm.org/show_bug.cgi?id=33869 This is the final of multiple patches that fix this bugzilla. Most of the patches are intended at refactoring the existent code. Reviews of the refactoring done to enable this change: https://reviews.llvm.org/D40330 https://reviews.llvm.org/D40331 https://reviews.llvm.org/D40332 https://reviews.llvm.org/D40333 Differential Revision: https://reviews.llvm.org/D40334 Change-Id: If95cbf1a3f5c7dccff8f1b22ecb397542147303d llvm-svn: 323096
172 lines
5.7 KiB
LLVM
172 lines
5.7 KiB
LLVM
; RUN: llc < %s -mtriple=x86_64-unknown-linux-gnu -mcpu=haswell -mattr=+lzcnt | FileCheck %s --check-prefix=HSW
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; RUN: llc < %s -mtriple=x86_64-unknown-linux-gnu -mcpu=skylake -mattr=+lzcnt | FileCheck %s --check-prefix=SKL
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; This tests a fix for bugzilla 33869 https://bugs.llvm.org/show_bug.cgi?id=33869
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declare i32 @llvm.ctpop.i32(i32)
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declare i64 @llvm.ctpop.i64(i64)
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declare i64 @llvm.ctlz.i64(i64, i1)
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declare i32 @llvm.cttz.i32(i32, i1)
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declare i64 @llvm.cttz.i64(i64, i1)
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declare i32 @llvm.ctlz.i32(i32, i1)
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define i32 @loopdep_popcnt32(i32* nocapture %x, double* nocapture %y) nounwind {
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entry:
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%vx = load i32, i32* %x
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br label %loop
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loop:
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%i = phi i32 [ 1, %entry ], [ %inc, %loop ]
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%s1 = phi i32 [ %vx, %entry ], [ %s2, %loop ]
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tail call void asm sideeffect "", "~{eax},~{ebx},~{ecx},~{edx},~{esi},~{edi},~{ebp},~{dirflag},~{fpsr},~{flags}"()
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%j = tail call i32 @llvm.ctpop.i32(i32 %i)
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%s2 = add i32 %s1, %j
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%inc = add nsw i32 %i, 1
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tail call void asm sideeffect "", "~{eax},~{ebx},~{ecx},~{edx},~{esi},~{edi},~{ebp},~{dirflag},~{fpsr},~{flags}"()
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%exitcond = icmp eq i32 %inc, 156250000
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br i1 %exitcond, label %ret, label %loop
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ret:
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ret i32 %s2
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;HSW-LABEL:@loopdep_popcnt32
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;HSW: xorl [[GPR0:%e[a-d]x]], [[GPR0]]
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;HSW-NEXT: popcntl {{.*}}, [[GPR0]]
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;SKL-LABEL:@loopdep_popcnt32
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;SKL: xorl [[GPR0:%e[a-d]x]], [[GPR0]]
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;SKL-NEXT: popcntl {{.*}}, [[GPR0]]
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}
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define i64 @loopdep_popcnt64(i64* nocapture %x, double* nocapture %y) nounwind {
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entry:
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%vx = load i64, i64* %x
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br label %loop
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loop:
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%i = phi i64 [ 1, %entry ], [ %inc, %loop ]
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%s1 = phi i64 [ %vx, %entry ], [ %s2, %loop ]
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tail call void asm sideeffect "", "~{eax},~{ebx},~{ecx},~{edx},~{esi},~{edi},~{ebp},~{dirflag},~{fpsr},~{flags}"()
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%j = tail call i64 @llvm.ctpop.i64(i64 %i)
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%s2 = add i64 %s1, %j
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%inc = add nsw i64 %i, 1
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tail call void asm sideeffect "", "~{eax},~{ebx},~{ecx},~{edx},~{esi},~{edi},~{ebp},~{dirflag},~{fpsr},~{flags}"()
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%exitcond = icmp eq i64 %inc, 156250000
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br i1 %exitcond, label %ret, label %loop
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ret:
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ret i64 %s2
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;HSW-LABEL:@loopdep_popcnt64
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;HSW: xorl %e[[GPR0:[a-d]x]], %e[[GPR0]]
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;HSW-NEXT: popcntq {{.*}}, %r[[GPR0]]
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;SKL-LABEL:@loopdep_popcnt64
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;SKL: xorl %e[[GPR0:[a-d]x]], %e[[GPR0]]
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;SKL-NEXT: popcntq {{.*}}, %r[[GPR0]]
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}
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define i32 @loopdep_tzct32(i32* nocapture %x, double* nocapture %y) nounwind {
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entry:
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%vx = load i32, i32* %x
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br label %loop
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loop:
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%i = phi i32 [ 1, %entry ], [ %inc, %loop ]
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%s1 = phi i32 [ %vx, %entry ], [ %s2, %loop ]
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tail call void asm sideeffect "", "~{eax},~{ebx},~{ecx},~{edx},~{esi},~{edi},~{ebp},~{dirflag},~{fpsr},~{flags}"()
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%j = call i32 @llvm.cttz.i32(i32 %i, i1 true)
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%s2 = add i32 %s1, %j
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%inc = add nsw i32 %i, 1
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tail call void asm sideeffect "", "~{eax},~{ebx},~{ecx},~{edx},~{esi},~{edi},~{ebp},~{dirflag},~{fpsr},~{flags}"()
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%exitcond = icmp eq i32 %inc, 156250000
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br i1 %exitcond, label %ret, label %loop
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ret:
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ret i32 %s2
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;HSW-LABEL:@loopdep_tzct32
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;HSW: xorl [[GPR0:%e[a-d]x]], [[GPR0]]
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;HSW-NEXT: tzcntl {{.*}}, [[GPR0]]
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; This false dependecy issue was fixed in Skylake
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;SKL-LABEL:@loopdep_tzct32
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;SKL-NOT: xor
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;SKL: tzcntl
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}
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define i64 @loopdep_tzct64(i64* nocapture %x, double* nocapture %y) nounwind {
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entry:
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%vx = load i64, i64* %x
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br label %loop
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loop:
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%i = phi i64 [ 1, %entry ], [ %inc, %loop ]
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%s1 = phi i64 [ %vx, %entry ], [ %s2, %loop ]
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tail call void asm sideeffect "", "~{eax},~{ebx},~{ecx},~{edx},~{esi},~{edi},~{ebp},~{dirflag},~{fpsr},~{flags}"()
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%j = tail call i64 @llvm.cttz.i64(i64 %i, i1 true)
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%s2 = add i64 %s1, %j
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%inc = add nsw i64 %i, 1
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tail call void asm sideeffect "", "~{eax},~{ebx},~{ecx},~{edx},~{esi},~{edi},~{ebp},~{dirflag},~{fpsr},~{flags}"()
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%exitcond = icmp eq i64 %inc, 156250000
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br i1 %exitcond, label %ret, label %loop
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ret:
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ret i64 %s2
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;HSW-LABEL:@loopdep_tzct64
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;HSW: xorl %e[[GPR0:[a-d]x]], %e[[GPR0]]
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;HSW-NEXT: tzcntq {{.*}}, %r[[GPR0]]
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; This false dependecy issue was fixed in Skylake
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;SKL-LABEL:@loopdep_tzct64
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;SKL-NOT: xor
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;SKL: tzcntq
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}
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define i32 @loopdep_lzct32(i32* nocapture %x, double* nocapture %y) nounwind {
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entry:
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%vx = load i32, i32* %x
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br label %loop
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loop:
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%i = phi i32 [ 1, %entry ], [ %inc, %loop ]
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%s1 = phi i32 [ %vx, %entry ], [ %s2, %loop ]
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tail call void asm sideeffect "", "~{eax},~{ebx},~{ecx},~{edx},~{esi},~{edi},~{ebp},~{dirflag},~{fpsr},~{flags}"()
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%j = call i32 @llvm.ctlz.i32(i32 %i, i1 true)
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%s2 = add i32 %s1, %j
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%inc = add nsw i32 %i, 1
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tail call void asm sideeffect "", "~{eax},~{ebx},~{ecx},~{edx},~{esi},~{edi},~{ebp},~{dirflag},~{fpsr},~{flags}"()
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%exitcond = icmp eq i32 %inc, 156250000
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br i1 %exitcond, label %ret, label %loop
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ret:
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ret i32 %s2
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;HSW-LABEL:@loopdep_lzct32
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;HSW: xorl [[GPR0:%e[a-d]x]], [[GPR0]]
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;HSW-NEXT: lzcntl {{.*}}, [[GPR0]]
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; This false dependecy issue was fixed in Skylake
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;SKL-LABEL:@loopdep_lzct32
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;SKL-NOT: xor
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;SKL: lzcntl
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}
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define i64 @loopdep_lzct64(i64* nocapture %x, double* nocapture %y) nounwind {
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entry:
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%vx = load i64, i64* %x
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br label %loop
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loop:
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%i = phi i64 [ 1, %entry ], [ %inc, %loop ]
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%s1 = phi i64 [ %vx, %entry ], [ %s2, %loop ]
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tail call void asm sideeffect "", "~{eax},~{ebx},~{ecx},~{edx},~{esi},~{edi},~{ebp},~{dirflag},~{fpsr},~{flags}"()
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%j = tail call i64 @llvm.ctlz.i64(i64 %i, i1 true)
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%s2 = add i64 %s1, %j
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%inc = add nsw i64 %i, 1
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tail call void asm sideeffect "", "~{eax},~{ebx},~{ecx},~{edx},~{esi},~{edi},~{ebp},~{dirflag},~{fpsr},~{flags}"()
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%exitcond = icmp eq i64 %inc, 156250000
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br i1 %exitcond, label %ret, label %loop
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ret:
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ret i64 %s2
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;HSW-LABEL:@loopdep_lzct64
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;HSW: xorl %e[[GPR0:[a-d]x]], %e[[GPR0]]
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;HSW-NEXT: lzcntq {{.*}}, %r[[GPR0]]
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; This false dependecy issue was fixed in Skylake
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;SKL-LABEL:@loopdep_lzct64
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;SKL-NOT: xor
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;SKL: lzcntq
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}
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