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325 lines
11 KiB
LLVM
325 lines
11 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse4.1 | FileCheck %s --check-prefix=CHECK --check-prefix=SSE
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx | FileCheck %s --check-prefix=CHECK --check-prefix=AVX --check-prefix=AVX1
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx2 | FileCheck %s --check-prefix=CHECK --check-prefix=AVX --check-prefix=AVX2
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; fold (urem undef, x) -> 0
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define i32 @combine_urem_undef0(i32 %x) {
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; CHECK-LABEL: combine_urem_undef0:
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; CHECK: # %bb.0:
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; CHECK-NEXT: xorl %eax, %eax
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; CHECK-NEXT: retq
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%1 = urem i32 undef, %x
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ret i32 %1
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}
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define <4 x i32> @combine_vec_urem_undef0(<4 x i32> %x) {
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; CHECK-LABEL: combine_vec_urem_undef0:
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; CHECK: # %bb.0:
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; CHECK-NEXT: retq
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%1 = urem <4 x i32> undef, %x
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ret <4 x i32> %1
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}
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; fold (urem x, undef) -> undef
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define i32 @combine_urem_undef1(i32 %x) {
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; CHECK-LABEL: combine_urem_undef1:
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; CHECK: # %bb.0:
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; CHECK-NEXT: retq
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%1 = urem i32 %x, undef
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ret i32 %1
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}
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define <4 x i32> @combine_vec_urem_undef1(<4 x i32> %x) {
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; CHECK-LABEL: combine_vec_urem_undef1:
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; CHECK: # %bb.0:
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; CHECK-NEXT: retq
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%1 = urem <4 x i32> %x, undef
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ret <4 x i32> %1
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}
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; fold (urem x, 1) -> 0
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define i32 @combine_urem_by_one(i32 %x) {
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; CHECK-LABEL: combine_urem_by_one:
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; CHECK: # %bb.0:
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; CHECK-NEXT: xorl %eax, %eax
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; CHECK-NEXT: retq
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%1 = urem i32 %x, 1
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ret i32 %1
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}
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define <4 x i32> @combine_vec_urem_by_one(<4 x i32> %x) {
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; SSE-LABEL: combine_vec_urem_by_one:
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; SSE: # %bb.0:
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; SSE-NEXT: xorps %xmm0, %xmm0
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; SSE-NEXT: retq
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;
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; AVX-LABEL: combine_vec_urem_by_one:
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; AVX: # %bb.0:
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; AVX-NEXT: vxorps %xmm0, %xmm0, %xmm0
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; AVX-NEXT: retq
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%1 = urem <4 x i32> %x, <i32 1, i32 1, i32 1, i32 1>
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ret <4 x i32> %1
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}
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; TODO fold (urem x, x) -> 0
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define i32 @combine_urem_dupe(i32 %x) {
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; CHECK-LABEL: combine_urem_dupe:
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; CHECK: # %bb.0:
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; CHECK-NEXT: xorl %edx, %edx
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; CHECK-NEXT: movl %edi, %eax
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; CHECK-NEXT: divl %edi
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; CHECK-NEXT: movl %edx, %eax
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; CHECK-NEXT: retq
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%1 = urem i32 %x, %x
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ret i32 %1
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}
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define <4 x i32> @combine_vec_urem_dupe(<4 x i32> %x) {
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; SSE-LABEL: combine_vec_urem_dupe:
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; SSE: # %bb.0:
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; SSE-NEXT: pextrd $1, %xmm0, %eax
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; SSE-NEXT: xorl %edx, %edx
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; SSE-NEXT: divl %eax
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; SSE-NEXT: movl %edx, %ecx
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; SSE-NEXT: movd %xmm0, %eax
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; SSE-NEXT: xorl %edx, %edx
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; SSE-NEXT: divl %eax
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; SSE-NEXT: movd %edx, %xmm1
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; SSE-NEXT: pinsrd $1, %ecx, %xmm1
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; SSE-NEXT: pextrd $2, %xmm0, %eax
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; SSE-NEXT: xorl %edx, %edx
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; SSE-NEXT: divl %eax
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; SSE-NEXT: pinsrd $2, %edx, %xmm1
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; SSE-NEXT: pextrd $3, %xmm0, %eax
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; SSE-NEXT: xorl %edx, %edx
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; SSE-NEXT: divl %eax
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; SSE-NEXT: pinsrd $3, %edx, %xmm1
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; SSE-NEXT: movdqa %xmm1, %xmm0
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; SSE-NEXT: retq
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;
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; AVX-LABEL: combine_vec_urem_dupe:
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; AVX: # %bb.0:
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; AVX-NEXT: vpextrd $1, %xmm0, %eax
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; AVX-NEXT: xorl %edx, %edx
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; AVX-NEXT: divl %eax
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; AVX-NEXT: movl %edx, %ecx
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; AVX-NEXT: vmovd %xmm0, %eax
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; AVX-NEXT: xorl %edx, %edx
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; AVX-NEXT: divl %eax
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; AVX-NEXT: vmovd %edx, %xmm1
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; AVX-NEXT: vpinsrd $1, %ecx, %xmm1, %xmm1
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; AVX-NEXT: vpextrd $2, %xmm0, %eax
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; AVX-NEXT: xorl %edx, %edx
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; AVX-NEXT: divl %eax
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; AVX-NEXT: vpinsrd $2, %edx, %xmm1, %xmm1
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; AVX-NEXT: vpextrd $3, %xmm0, %eax
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; AVX-NEXT: xorl %edx, %edx
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; AVX-NEXT: divl %eax
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; AVX-NEXT: vpinsrd $3, %edx, %xmm1, %xmm0
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; AVX-NEXT: retq
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%1 = urem <4 x i32> %x, %x
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ret <4 x i32> %1
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}
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; fold (urem x, pow2) -> (and x, (pow2-1))
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define <4 x i32> @combine_vec_urem_by_pow2a(<4 x i32> %x) {
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; SSE-LABEL: combine_vec_urem_by_pow2a:
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; SSE: # %bb.0:
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; SSE-NEXT: andps {{.*}}(%rip), %xmm0
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; SSE-NEXT: retq
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;
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; AVX1-LABEL: combine_vec_urem_by_pow2a:
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; AVX1: # %bb.0:
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; AVX1-NEXT: vandps {{.*}}(%rip), %xmm0, %xmm0
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; AVX1-NEXT: retq
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;
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; AVX2-LABEL: combine_vec_urem_by_pow2a:
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; AVX2: # %bb.0:
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; AVX2-NEXT: vbroadcastss {{.*#+}} xmm1 = [3,3,3,3]
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; AVX2-NEXT: vandps %xmm1, %xmm0, %xmm0
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; AVX2-NEXT: retq
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%1 = urem <4 x i32> %x, <i32 4, i32 4, i32 4, i32 4>
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ret <4 x i32> %1
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}
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define <4 x i32> @combine_vec_urem_by_pow2b(<4 x i32> %x) {
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; SSE-LABEL: combine_vec_urem_by_pow2b:
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; SSE: # %bb.0:
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; SSE-NEXT: andps {{.*}}(%rip), %xmm0
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; SSE-NEXT: retq
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;
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; AVX-LABEL: combine_vec_urem_by_pow2b:
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; AVX: # %bb.0:
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; AVX-NEXT: vandps {{.*}}(%rip), %xmm0, %xmm0
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; AVX-NEXT: retq
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%1 = urem <4 x i32> %x, <i32 1, i32 4, i32 8, i32 16>
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ret <4 x i32> %1
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}
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define <4 x i32> @combine_vec_urem_by_pow2c(<4 x i32> %x, <4 x i32> %y) {
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; SSE-LABEL: combine_vec_urem_by_pow2c:
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; SSE: # %bb.0:
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; SSE-NEXT: pslld $23, %xmm1
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; SSE-NEXT: paddd {{.*}}(%rip), %xmm1
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; SSE-NEXT: cvttps2dq %xmm1, %xmm1
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; SSE-NEXT: pcmpeqd %xmm2, %xmm2
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; SSE-NEXT: paddd %xmm1, %xmm2
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; SSE-NEXT: pand %xmm2, %xmm0
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; SSE-NEXT: retq
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;
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; AVX1-LABEL: combine_vec_urem_by_pow2c:
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; AVX1: # %bb.0:
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; AVX1-NEXT: vpslld $23, %xmm1, %xmm1
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; AVX1-NEXT: vpaddd {{.*}}(%rip), %xmm1, %xmm1
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; AVX1-NEXT: vcvttps2dq %xmm1, %xmm1
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; AVX1-NEXT: vpcmpeqd %xmm2, %xmm2, %xmm2
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; AVX1-NEXT: vpaddd %xmm2, %xmm1, %xmm1
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; AVX1-NEXT: vpand %xmm1, %xmm0, %xmm0
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; AVX1-NEXT: retq
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;
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; AVX2-LABEL: combine_vec_urem_by_pow2c:
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; AVX2: # %bb.0:
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; AVX2-NEXT: vpbroadcastd {{.*#+}} xmm2 = [1,1,1,1]
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; AVX2-NEXT: vpsllvd %xmm1, %xmm2, %xmm1
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; AVX2-NEXT: vpcmpeqd %xmm2, %xmm2, %xmm2
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; AVX2-NEXT: vpaddd %xmm2, %xmm1, %xmm1
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; AVX2-NEXT: vpand %xmm1, %xmm0, %xmm0
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; AVX2-NEXT: retq
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%1 = shl <4 x i32> <i32 1, i32 1, i32 1, i32 1>, %y
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%2 = urem <4 x i32> %x, %1
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ret <4 x i32> %2
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}
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define <4 x i32> @combine_vec_urem_by_pow2d(<4 x i32> %x, <4 x i32> %y) {
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; SSE-LABEL: combine_vec_urem_by_pow2d:
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; SSE: # %bb.0:
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; SSE-NEXT: movdqa %xmm1, %xmm2
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; SSE-NEXT: psrldq {{.*#+}} xmm2 = xmm2[12,13,14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
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; SSE-NEXT: movdqa {{.*#+}} xmm3 = [2147483648,2147483648,2147483648,2147483648]
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; SSE-NEXT: movdqa %xmm3, %xmm4
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; SSE-NEXT: psrld %xmm2, %xmm4
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; SSE-NEXT: movdqa %xmm1, %xmm2
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; SSE-NEXT: psrlq $32, %xmm2
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; SSE-NEXT: movdqa %xmm3, %xmm5
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; SSE-NEXT: psrld %xmm2, %xmm5
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; SSE-NEXT: pblendw {{.*#+}} xmm5 = xmm5[0,1,2,3],xmm4[4,5,6,7]
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; SSE-NEXT: pxor %xmm2, %xmm2
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; SSE-NEXT: pmovzxdq {{.*#+}} xmm4 = xmm1[0],zero,xmm1[1],zero
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; SSE-NEXT: punpckhdq {{.*#+}} xmm1 = xmm1[2],xmm2[2],xmm1[3],xmm2[3]
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; SSE-NEXT: movdqa %xmm3, %xmm2
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; SSE-NEXT: psrld %xmm1, %xmm2
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; SSE-NEXT: psrld %xmm4, %xmm3
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; SSE-NEXT: pblendw {{.*#+}} xmm3 = xmm3[0,1,2,3],xmm2[4,5,6,7]
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; SSE-NEXT: pblendw {{.*#+}} xmm3 = xmm3[0,1],xmm5[2,3],xmm3[4,5],xmm5[6,7]
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; SSE-NEXT: pcmpeqd %xmm1, %xmm1
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; SSE-NEXT: paddd %xmm3, %xmm1
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; SSE-NEXT: pand %xmm1, %xmm0
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; SSE-NEXT: retq
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;
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; AVX1-LABEL: combine_vec_urem_by_pow2d:
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; AVX1: # %bb.0:
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; AVX1-NEXT: vpsrldq {{.*#+}} xmm2 = xmm1[12,13,14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
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; AVX1-NEXT: vmovdqa {{.*#+}} xmm3 = [2147483648,2147483648,2147483648,2147483648]
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; AVX1-NEXT: vpsrld %xmm2, %xmm3, %xmm2
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; AVX1-NEXT: vpsrlq $32, %xmm1, %xmm4
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; AVX1-NEXT: vpsrld %xmm4, %xmm3, %xmm4
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; AVX1-NEXT: vpblendw {{.*#+}} xmm2 = xmm4[0,1,2,3],xmm2[4,5,6,7]
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; AVX1-NEXT: vpxor %xmm4, %xmm4, %xmm4
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; AVX1-NEXT: vpunpckhdq {{.*#+}} xmm4 = xmm1[2],xmm4[2],xmm1[3],xmm4[3]
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; AVX1-NEXT: vpsrld %xmm4, %xmm3, %xmm4
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; AVX1-NEXT: vpmovzxdq {{.*#+}} xmm1 = xmm1[0],zero,xmm1[1],zero
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; AVX1-NEXT: vpsrld %xmm1, %xmm3, %xmm1
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; AVX1-NEXT: vpblendw {{.*#+}} xmm1 = xmm1[0,1,2,3],xmm4[4,5,6,7]
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; AVX1-NEXT: vpblendw {{.*#+}} xmm1 = xmm1[0,1],xmm2[2,3],xmm1[4,5],xmm2[6,7]
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; AVX1-NEXT: vpcmpeqd %xmm2, %xmm2, %xmm2
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; AVX1-NEXT: vpaddd %xmm2, %xmm1, %xmm1
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; AVX1-NEXT: vpand %xmm1, %xmm0, %xmm0
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; AVX1-NEXT: retq
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;
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; AVX2-LABEL: combine_vec_urem_by_pow2d:
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; AVX2: # %bb.0:
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; AVX2-NEXT: vpbroadcastd {{.*#+}} xmm2 = [2147483648,2147483648,2147483648,2147483648]
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; AVX2-NEXT: vpsrlvd %xmm1, %xmm2, %xmm1
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; AVX2-NEXT: vpcmpeqd %xmm2, %xmm2, %xmm2
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; AVX2-NEXT: vpaddd %xmm2, %xmm1, %xmm1
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; AVX2-NEXT: vpand %xmm1, %xmm0, %xmm0
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; AVX2-NEXT: retq
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%1 = lshr <4 x i32> <i32 -2147483648, i32 -2147483648, i32 -2147483648, i32 -2147483648>, %y
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%2 = urem <4 x i32> %x, %1
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ret <4 x i32> %2
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}
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; fold (urem x, (shl pow2, y)) -> (and x, (add (shl pow2, y), -1))
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define <4 x i32> @combine_vec_urem_by_shl_pow2a(<4 x i32> %x, <4 x i32> %y) {
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; SSE-LABEL: combine_vec_urem_by_shl_pow2a:
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; SSE: # %bb.0:
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; SSE-NEXT: pslld $23, %xmm1
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; SSE-NEXT: paddd {{.*}}(%rip), %xmm1
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; SSE-NEXT: cvttps2dq %xmm1, %xmm1
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; SSE-NEXT: pslld $2, %xmm1
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; SSE-NEXT: pcmpeqd %xmm2, %xmm2
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; SSE-NEXT: paddd %xmm1, %xmm2
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; SSE-NEXT: pand %xmm2, %xmm0
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; SSE-NEXT: retq
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;
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; AVX1-LABEL: combine_vec_urem_by_shl_pow2a:
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; AVX1: # %bb.0:
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; AVX1-NEXT: vpslld $23, %xmm1, %xmm1
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; AVX1-NEXT: vpaddd {{.*}}(%rip), %xmm1, %xmm1
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; AVX1-NEXT: vcvttps2dq %xmm1, %xmm1
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; AVX1-NEXT: vpslld $2, %xmm1, %xmm1
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; AVX1-NEXT: vpcmpeqd %xmm2, %xmm2, %xmm2
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; AVX1-NEXT: vpaddd %xmm2, %xmm1, %xmm1
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; AVX1-NEXT: vpand %xmm1, %xmm0, %xmm0
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; AVX1-NEXT: retq
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;
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; AVX2-LABEL: combine_vec_urem_by_shl_pow2a:
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; AVX2: # %bb.0:
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; AVX2-NEXT: vpbroadcastd {{.*#+}} xmm2 = [4,4,4,4]
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; AVX2-NEXT: vpsllvd %xmm1, %xmm2, %xmm1
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; AVX2-NEXT: vpcmpeqd %xmm2, %xmm2, %xmm2
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; AVX2-NEXT: vpaddd %xmm2, %xmm1, %xmm1
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; AVX2-NEXT: vpand %xmm1, %xmm0, %xmm0
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; AVX2-NEXT: retq
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%1 = shl <4 x i32> <i32 4, i32 4, i32 4, i32 4>, %y
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%2 = urem <4 x i32> %x, %1
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ret <4 x i32> %2
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}
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define <4 x i32> @combine_vec_urem_by_shl_pow2b(<4 x i32> %x, <4 x i32> %y) {
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; SSE-LABEL: combine_vec_urem_by_shl_pow2b:
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; SSE: # %bb.0:
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; SSE-NEXT: pslld $23, %xmm1
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; SSE-NEXT: paddd {{.*}}(%rip), %xmm1
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; SSE-NEXT: cvttps2dq %xmm1, %xmm1
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; SSE-NEXT: pmulld {{.*}}(%rip), %xmm1
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; SSE-NEXT: pcmpeqd %xmm2, %xmm2
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; SSE-NEXT: paddd %xmm1, %xmm2
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; SSE-NEXT: pand %xmm2, %xmm0
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; SSE-NEXT: retq
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;
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; AVX1-LABEL: combine_vec_urem_by_shl_pow2b:
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; AVX1: # %bb.0:
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; AVX1-NEXT: vpslld $23, %xmm1, %xmm1
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; AVX1-NEXT: vpaddd {{.*}}(%rip), %xmm1, %xmm1
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; AVX1-NEXT: vcvttps2dq %xmm1, %xmm1
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; AVX1-NEXT: vpmulld {{.*}}(%rip), %xmm1, %xmm1
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; AVX1-NEXT: vpcmpeqd %xmm2, %xmm2, %xmm2
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; AVX1-NEXT: vpaddd %xmm2, %xmm1, %xmm1
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; AVX1-NEXT: vpand %xmm1, %xmm0, %xmm0
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; AVX1-NEXT: retq
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;
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; AVX2-LABEL: combine_vec_urem_by_shl_pow2b:
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; AVX2: # %bb.0:
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; AVX2-NEXT: vmovdqa {{.*#+}} xmm2 = [1,4,8,16]
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; AVX2-NEXT: vpsllvd %xmm1, %xmm2, %xmm1
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; AVX2-NEXT: vpcmpeqd %xmm2, %xmm2, %xmm2
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; AVX2-NEXT: vpaddd %xmm2, %xmm1, %xmm1
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; AVX2-NEXT: vpand %xmm1, %xmm0, %xmm0
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; AVX2-NEXT: retq
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%1 = shl <4 x i32> <i32 1, i32 4, i32 8, i32 16>, %y
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%2 = urem <4 x i32> %x, %1
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ret <4 x i32> %2
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}
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