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961f3df27b
As part of the unification of the debug format and the MIR format, always print registers as lowercase. * Only debug printing is affected. It now follows MIR. Differential Revision: https://reviews.llvm.org/D40417 llvm-svn: 319187
45 lines
1.2 KiB
LLVM
45 lines
1.2 KiB
LLVM
; RUN: llc < %s -tailcallopt -mtriple=i686-linux-gnu | FileCheck %s
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; Test the GHC call convention works (x86-32)
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@base = external global i32 ; assigned to register: ebx
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@sp = external global i32 ; assigned to register: ebp
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@hp = external global i32 ; assigned to register: edi
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@r1 = external global i32 ; assigned to register: esi
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define void @zap(i32 %a, i32 %b) nounwind {
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entry:
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; CHECK: movl {{[0-9]*}}(%esp), %ebx
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; CHECK-NEXT: movl {{[0-9]*}}(%esp), %ebp
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; CHECK-NEXT: calll addtwo
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%0 = call ghccc i32 @addtwo(i32 %a, i32 %b)
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; CHECK: calll foo
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call void @foo() nounwind
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ret void
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}
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define ghccc i32 @addtwo(i32 %x, i32 %y) nounwind {
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entry:
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; CHECK: leal (%ebx,%ebp), %eax
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%0 = add i32 %x, %y
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; CHECK-NEXT: ret
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ret i32 %0
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}
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define ghccc void @foo() nounwind {
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entry:
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; CHECK: movl r1, %esi
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; CHECK-NEXT: movl hp, %edi
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; CHECK-NEXT: movl sp, %ebp
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; CHECK-NEXT: movl base, %ebx
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%0 = load i32, i32* @r1
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%1 = load i32, i32* @hp
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%2 = load i32, i32* @sp
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%3 = load i32, i32* @base
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; CHECK: jmp bar
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tail call ghccc void @bar( i32 %3, i32 %2, i32 %1, i32 %0 ) nounwind
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ret void
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}
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declare ghccc void @bar(i32, i32, i32, i32)
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