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55d27cdd65
Updated the scheduling information for the Haswell subtarget with the following changes: Regrouped the instructions after adding appropriate load + store latencies. Added scheduling for missing instructions such as the GATHER instrs. The changes were made after revisiting the latencies impact of all memory uOps. Reviewers: RKSimon, zvi, craig.topper, apilipenko Differential Revision: https://reviews.llvm.org/D40021 Change-Id: Iaf6c1f5169add1552845a8a566af4e5a359217a7 llvm-svn: 320137
213 lines
8.9 KiB
LLVM
213 lines
8.9 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -print-schedule -mcpu=x86-64 -mattr=+popcnt | FileCheck %s --check-prefix=CHECK --check-prefix=GENERIC
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -print-schedule -mcpu=slm | FileCheck %s --check-prefix=CHECK --check-prefix=SLM
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -print-schedule -mcpu=goldmont | FileCheck %s --check-prefix=CHECK --check-prefix=SLM
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -print-schedule -mcpu=sandybridge | FileCheck %s --check-prefix=CHECK --check-prefix=SANDY
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -print-schedule -mcpu=ivybridge | FileCheck %s --check-prefix=CHECK --check-prefix=SANDY
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -print-schedule -mcpu=haswell | FileCheck %s --check-prefix=CHECK --check-prefix=HASWELL
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -print-schedule -mcpu=broadwell | FileCheck %s --check-prefix=CHECK --check-prefix=BROADWELL
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -print-schedule -mcpu=skylake | FileCheck %s --check-prefix=CHECK --check-prefix=SKYLAKE
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -print-schedule -mcpu=knl | FileCheck %s --check-prefix=CHECK --check-prefix=HASWELL
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -print-schedule -mcpu=btver2 | FileCheck %s --check-prefix=CHECK --check-prefix=BTVER2
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -print-schedule -mcpu=znver1 | FileCheck %s --check-prefix=CHECK --check-prefix=ZNVER1
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define i16 @test_ctpop_i16(i16 zeroext %a0, i16 *%a1) {
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; GENERIC-LABEL: test_ctpop_i16:
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; GENERIC: # %bb.0:
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; GENERIC-NEXT: popcntw (%rsi), %cx # sched: [9:1.00]
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; GENERIC-NEXT: popcntw %di, %ax # sched: [3:1.00]
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; GENERIC-NEXT: orl %ecx, %eax # sched: [1:0.33]
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; GENERIC-NEXT: # kill: def %ax killed %ax killed %eax
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; GENERIC-NEXT: retq # sched: [1:1.00]
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;
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; SLM-LABEL: test_ctpop_i16:
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; SLM: # %bb.0:
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; SLM-NEXT: popcntw (%rsi), %cx # sched: [6:1.00]
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; SLM-NEXT: popcntw %di, %ax # sched: [3:1.00]
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; SLM-NEXT: orl %ecx, %eax # sched: [1:0.50]
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; SLM-NEXT: # kill: def %ax killed %ax killed %eax
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; SLM-NEXT: retq # sched: [4:1.00]
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;
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; SANDY-LABEL: test_ctpop_i16:
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; SANDY: # %bb.0:
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; SANDY-NEXT: popcntw (%rsi), %cx # sched: [9:1.00]
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; SANDY-NEXT: popcntw %di, %ax # sched: [3:1.00]
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; SANDY-NEXT: orl %ecx, %eax # sched: [1:0.33]
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; SANDY-NEXT: # kill: def %ax killed %ax killed %eax
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; SANDY-NEXT: retq # sched: [1:1.00]
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;
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; HASWELL-LABEL: test_ctpop_i16:
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; HASWELL: # %bb.0:
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; HASWELL-NEXT: popcntw (%rsi), %cx # sched: [8:1.00]
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; HASWELL-NEXT: popcntw %di, %ax # sched: [3:1.00]
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; HASWELL-NEXT: orl %ecx, %eax # sched: [1:0.25]
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; HASWELL-NEXT: # kill: def %ax killed %ax killed %eax
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; HASWELL-NEXT: retq # sched: [7:1.00]
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;
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; BROADWELL-LABEL: test_ctpop_i16:
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; BROADWELL: # %bb.0:
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; BROADWELL-NEXT: popcntw (%rsi), %cx # sched: [8:1.00]
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; BROADWELL-NEXT: popcntw %di, %ax # sched: [3:1.00]
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; BROADWELL-NEXT: orl %ecx, %eax # sched: [1:0.25]
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; BROADWELL-NEXT: # kill: def %ax killed %ax killed %eax
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; BROADWELL-NEXT: retq # sched: [7:1.00]
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;
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; SKYLAKE-LABEL: test_ctpop_i16:
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; SKYLAKE: # %bb.0:
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; SKYLAKE-NEXT: popcntw (%rsi), %cx # sched: [8:1.00]
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; SKYLAKE-NEXT: popcntw %di, %ax # sched: [3:1.00]
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; SKYLAKE-NEXT: orl %ecx, %eax # sched: [1:0.25]
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; SKYLAKE-NEXT: # kill: def %ax killed %ax killed %eax
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; SKYLAKE-NEXT: retq # sched: [7:1.00]
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;
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; BTVER2-LABEL: test_ctpop_i16:
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; BTVER2: # %bb.0:
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; BTVER2-NEXT: popcntw (%rsi), %cx # sched: [8:1.00]
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; BTVER2-NEXT: popcntw %di, %ax # sched: [3:1.00]
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; BTVER2-NEXT: orl %ecx, %eax # sched: [1:0.50]
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; BTVER2-NEXT: # kill: def %ax killed %ax killed %eax
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; BTVER2-NEXT: retq # sched: [4:1.00]
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;
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; ZNVER1-LABEL: test_ctpop_i16:
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; ZNVER1: # %bb.0:
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; ZNVER1-NEXT: popcntw (%rsi), %cx # sched: [10:1.00]
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; ZNVER1-NEXT: popcntw %di, %ax # sched: [3:1.00]
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; ZNVER1-NEXT: orl %ecx, %eax # sched: [1:0.25]
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; ZNVER1-NEXT: # kill: def %ax killed %ax killed %eax
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; ZNVER1-NEXT: retq # sched: [1:0.50]
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%1 = load i16, i16 *%a1
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%2 = tail call i16 @llvm.ctpop.i16( i16 %1 )
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%3 = tail call i16 @llvm.ctpop.i16( i16 %a0 )
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%4 = or i16 %2, %3
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ret i16 %4
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}
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declare i16 @llvm.ctpop.i16(i16)
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define i32 @test_ctpop_i32(i32 %a0, i32 *%a1) {
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; GENERIC-LABEL: test_ctpop_i32:
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; GENERIC: # %bb.0:
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; GENERIC-NEXT: popcntl (%rsi), %ecx # sched: [9:1.00]
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; GENERIC-NEXT: popcntl %edi, %eax # sched: [3:1.00]
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; GENERIC-NEXT: orl %ecx, %eax # sched: [1:0.33]
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; GENERIC-NEXT: retq # sched: [1:1.00]
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;
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; SLM-LABEL: test_ctpop_i32:
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; SLM: # %bb.0:
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; SLM-NEXT: popcntl (%rsi), %ecx # sched: [6:1.00]
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; SLM-NEXT: popcntl %edi, %eax # sched: [3:1.00]
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; SLM-NEXT: orl %ecx, %eax # sched: [1:0.50]
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; SLM-NEXT: retq # sched: [4:1.00]
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;
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; SANDY-LABEL: test_ctpop_i32:
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; SANDY: # %bb.0:
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; SANDY-NEXT: popcntl (%rsi), %ecx # sched: [9:1.00]
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; SANDY-NEXT: popcntl %edi, %eax # sched: [3:1.00]
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; SANDY-NEXT: orl %ecx, %eax # sched: [1:0.33]
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; SANDY-NEXT: retq # sched: [1:1.00]
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;
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; HASWELL-LABEL: test_ctpop_i32:
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; HASWELL: # %bb.0:
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; HASWELL-NEXT: popcntl (%rsi), %ecx # sched: [8:1.00]
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; HASWELL-NEXT: popcntl %edi, %eax # sched: [3:1.00]
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; HASWELL-NEXT: orl %ecx, %eax # sched: [1:0.25]
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; HASWELL-NEXT: retq # sched: [7:1.00]
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;
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; BROADWELL-LABEL: test_ctpop_i32:
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; BROADWELL: # %bb.0:
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; BROADWELL-NEXT: popcntl (%rsi), %ecx # sched: [8:1.00]
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; BROADWELL-NEXT: popcntl %edi, %eax # sched: [3:1.00]
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; BROADWELL-NEXT: orl %ecx, %eax # sched: [1:0.25]
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; BROADWELL-NEXT: retq # sched: [7:1.00]
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;
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; SKYLAKE-LABEL: test_ctpop_i32:
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; SKYLAKE: # %bb.0:
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; SKYLAKE-NEXT: popcntl (%rsi), %ecx # sched: [8:1.00]
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; SKYLAKE-NEXT: popcntl %edi, %eax # sched: [3:1.00]
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; SKYLAKE-NEXT: orl %ecx, %eax # sched: [1:0.25]
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; SKYLAKE-NEXT: retq # sched: [7:1.00]
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;
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; BTVER2-LABEL: test_ctpop_i32:
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; BTVER2: # %bb.0:
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; BTVER2-NEXT: popcntl (%rsi), %ecx # sched: [8:1.00]
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; BTVER2-NEXT: popcntl %edi, %eax # sched: [3:1.00]
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; BTVER2-NEXT: orl %ecx, %eax # sched: [1:0.50]
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; BTVER2-NEXT: retq # sched: [4:1.00]
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;
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; ZNVER1-LABEL: test_ctpop_i32:
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; ZNVER1: # %bb.0:
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; ZNVER1-NEXT: popcntl (%rsi), %ecx # sched: [10:1.00]
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; ZNVER1-NEXT: popcntl %edi, %eax # sched: [3:1.00]
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; ZNVER1-NEXT: orl %ecx, %eax # sched: [1:0.25]
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; ZNVER1-NEXT: retq # sched: [1:0.50]
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%1 = load i32, i32 *%a1
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%2 = tail call i32 @llvm.ctpop.i32( i32 %1 )
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%3 = tail call i32 @llvm.ctpop.i32( i32 %a0 )
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%4 = or i32 %2, %3
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ret i32 %4
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}
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declare i32 @llvm.ctpop.i32(i32)
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define i64 @test_ctpop_i64(i64 %a0, i64 *%a1) {
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; GENERIC-LABEL: test_ctpop_i64:
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; GENERIC: # %bb.0:
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; GENERIC-NEXT: popcntq (%rsi), %rcx # sched: [9:1.00]
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; GENERIC-NEXT: popcntq %rdi, %rax # sched: [3:1.00]
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; GENERIC-NEXT: orq %rcx, %rax # sched: [1:0.33]
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; GENERIC-NEXT: retq # sched: [1:1.00]
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;
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; SLM-LABEL: test_ctpop_i64:
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; SLM: # %bb.0:
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; SLM-NEXT: popcntq (%rsi), %rcx # sched: [6:1.00]
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; SLM-NEXT: popcntq %rdi, %rax # sched: [3:1.00]
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; SLM-NEXT: orq %rcx, %rax # sched: [1:0.50]
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; SLM-NEXT: retq # sched: [4:1.00]
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;
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; SANDY-LABEL: test_ctpop_i64:
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; SANDY: # %bb.0:
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; SANDY-NEXT: popcntq (%rsi), %rcx # sched: [9:1.00]
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; SANDY-NEXT: popcntq %rdi, %rax # sched: [3:1.00]
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; SANDY-NEXT: orq %rcx, %rax # sched: [1:0.33]
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; SANDY-NEXT: retq # sched: [1:1.00]
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;
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; HASWELL-LABEL: test_ctpop_i64:
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; HASWELL: # %bb.0:
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; HASWELL-NEXT: popcntq (%rsi), %rcx # sched: [8:1.00]
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; HASWELL-NEXT: popcntq %rdi, %rax # sched: [3:1.00]
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; HASWELL-NEXT: orq %rcx, %rax # sched: [1:0.25]
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; HASWELL-NEXT: retq # sched: [7:1.00]
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;
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; BROADWELL-LABEL: test_ctpop_i64:
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; BROADWELL: # %bb.0:
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; BROADWELL-NEXT: popcntq (%rsi), %rcx # sched: [8:1.00]
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; BROADWELL-NEXT: popcntq %rdi, %rax # sched: [3:1.00]
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; BROADWELL-NEXT: orq %rcx, %rax # sched: [1:0.25]
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; BROADWELL-NEXT: retq # sched: [7:1.00]
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;
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; SKYLAKE-LABEL: test_ctpop_i64:
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; SKYLAKE: # %bb.0:
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; SKYLAKE-NEXT: popcntq (%rsi), %rcx # sched: [8:1.00]
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; SKYLAKE-NEXT: popcntq %rdi, %rax # sched: [3:1.00]
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; SKYLAKE-NEXT: orq %rcx, %rax # sched: [1:0.25]
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; SKYLAKE-NEXT: retq # sched: [7:1.00]
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;
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; BTVER2-LABEL: test_ctpop_i64:
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; BTVER2: # %bb.0:
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; BTVER2-NEXT: popcntq (%rsi), %rcx # sched: [8:1.00]
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; BTVER2-NEXT: popcntq %rdi, %rax # sched: [3:1.00]
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; BTVER2-NEXT: orq %rcx, %rax # sched: [1:0.50]
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; BTVER2-NEXT: retq # sched: [4:1.00]
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;
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; ZNVER1-LABEL: test_ctpop_i64:
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; ZNVER1: # %bb.0:
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; ZNVER1-NEXT: popcntq (%rsi), %rcx # sched: [10:1.00]
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; ZNVER1-NEXT: popcntq %rdi, %rax # sched: [3:1.00]
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; ZNVER1-NEXT: orq %rcx, %rax # sched: [1:0.25]
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; ZNVER1-NEXT: retq # sched: [1:0.50]
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%1 = load i64, i64 *%a1
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%2 = tail call i64 @llvm.ctpop.i64( i64 %1 )
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%3 = tail call i64 @llvm.ctpop.i64( i64 %a0 )
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%4 = or i64 %2, %3
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ret i64 %4
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}
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declare i64 @llvm.ctpop.i64(i64)
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