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1b514619dd
* The method getRegAllocationHints() is now of bool type instead of void. If true is returned, regalloc (AllocationOrder) will *only* try to allocate the hints, as opposed to merely trying them before non-hinted registers. * TargetRegisterInfo::getRegAllocationHints() is implemented for SystemZ with an increase in number of LOCRs. In this case, it is desired to force the hints even though there is a slight increase in spilling, because if a non-hinted register would be allocated, the LOCRMux pseudo would have to be expanded with a jump sequence. The LOCR (Load On Condition) SystemZ instruction must have both operands in either the low or high part of the 64 bit register. Reviewers: Quentin Colombet and Ulrich Weigand https://reviews.llvm.org/D36795 llvm-svn: 317879
97 lines
2.9 KiB
C++
97 lines
2.9 KiB
C++
//===-- llvm/CodeGen/AllocationOrder.h - Allocation Order -*- C++ -*-------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements an allocation order for virtual registers.
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//
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// The preferred allocation order for a virtual register depends on allocation
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// hints and target hooks. The AllocationOrder class encapsulates all of that.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_CODEGEN_ALLOCATIONORDER_H
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#define LLVM_LIB_CODEGEN_ALLOCATIONORDER_H
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#include "llvm/ADT/ArrayRef.h"
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#include "llvm/ADT/STLExtras.h"
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#include "llvm/MC/MCRegisterInfo.h"
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namespace llvm {
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class RegisterClassInfo;
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class VirtRegMap;
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class LiveRegMatrix;
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class LLVM_LIBRARY_VISIBILITY AllocationOrder {
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SmallVector<MCPhysReg, 16> Hints;
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ArrayRef<MCPhysReg> Order;
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int Pos;
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// If HardHints is true, *only* Hints will be returned.
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bool HardHints;
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public:
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/// Create a new AllocationOrder for VirtReg.
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/// @param VirtReg Virtual register to allocate for.
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/// @param VRM Virtual register map for function.
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/// @param RegClassInfo Information about reserved and allocatable registers.
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AllocationOrder(unsigned VirtReg,
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const VirtRegMap &VRM,
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const RegisterClassInfo &RegClassInfo,
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const LiveRegMatrix *Matrix);
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/// Get the allocation order without reordered hints.
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ArrayRef<MCPhysReg> getOrder() const { return Order; }
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/// Return the next physical register in the allocation order, or 0.
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/// It is safe to call next() again after it returned 0, it will keep
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/// returning 0 until rewind() is called.
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unsigned next(unsigned Limit = 0) {
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if (Pos < 0)
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return Hints.end()[Pos++];
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if (HardHints)
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return 0;
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if (!Limit)
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Limit = Order.size();
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while (Pos < int(Limit)) {
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unsigned Reg = Order[Pos++];
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if (!isHint(Reg))
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return Reg;
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}
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return 0;
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}
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/// As next(), but allow duplicates to be returned, and stop before the
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/// Limit'th register in the RegisterClassInfo allocation order.
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///
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/// This can produce more than Limit registers if there are hints.
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unsigned nextWithDups(unsigned Limit) {
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if (Pos < 0)
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return Hints.end()[Pos++];
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if (HardHints)
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return 0;
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if (Pos < int(Limit))
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return Order[Pos++];
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return 0;
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}
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/// Start over from the beginning.
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void rewind() { Pos = -int(Hints.size()); }
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/// Return true if the last register returned from next() was a preferred register.
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bool isHint() const { return Pos <= 0; }
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/// Return true if PhysReg is a preferred register.
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bool isHint(unsigned PhysReg) const { return is_contained(Hints, PhysReg); }
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};
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} // end namespace llvm
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#endif
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