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Summary: We don't have control/verify what will be the RHS of the division, so it might happen to be zero, causing UB. Reviewers: Vasilis, RKSimon, ABataev Reviewed By: ABataev Subscribers: vporpo, ABataev, hiraditya, llvm-commits, vdmitrie Tags: #llvm Differential Revision: https://reviews.llvm.org/D72740 |
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AArch64 | ||
AMDGPU | ||
ARM | ||
NVPTX | ||
PowerPC | ||
SystemZ | ||
X86 | ||
XCore | ||
int_sideeffect.ll |