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708 lines
25 KiB
C++
708 lines
25 KiB
C++
//===- MipsInstrInfo.td - Mips Register defs --------------------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// Instruction format superclass
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//===----------------------------------------------------------------------===//
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include "MipsInstrFormats.td"
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//===----------------------------------------------------------------------===//
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// Mips profiles and nodes
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//===----------------------------------------------------------------------===//
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def SDT_MipsRet : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
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def SDT_MipsJmpLink : SDTypeProfile<0, 1, [SDTCisVT<0, iPTR>]>;
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def SDT_MipsSelectCC : SDTypeProfile<1, 3, [SDTCisSameAs<0, 2>,
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SDTCisSameAs<2, 3>, SDTCisInt<1>]>;
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def SDT_MipsCMov : SDTypeProfile<1, 4, [SDTCisSameAs<0, 1>,
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SDTCisSameAs<1, 2>, SDTCisSameAs<3, 4>,
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SDTCisInt<4>]>;
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def SDT_MipsCallSeqStart : SDCallSeqStart<[SDTCisVT<0, i32>]>;
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def SDT_MipsCallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i32>, SDTCisVT<1, i32>]>;
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// Call
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def MipsJmpLink : SDNode<"MipsISD::JmpLink",SDT_MipsJmpLink, [SDNPHasChain,
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SDNPOutFlag]>;
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// Hi and Lo nodes are used to handle global addresses. Used on
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// MipsISelLowering to lower stuff like GlobalAddress, ExternalSymbol
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// static model. (nothing to do with Mips Registers Hi and Lo)
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def MipsHi : SDNode<"MipsISD::Hi", SDTIntUnaryOp>;
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def MipsLo : SDNode<"MipsISD::Lo", SDTIntUnaryOp>;
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def MipsGPRel : SDNode<"MipsISD::GPRel", SDTIntUnaryOp>;
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// Return
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def MipsRet : SDNode<"MipsISD::Ret", SDT_MipsRet, [SDNPHasChain,
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SDNPOptInFlag]>;
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// These are target-independent nodes, but have target-specific formats.
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def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_MipsCallSeqStart,
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[SDNPHasChain, SDNPOutFlag]>;
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def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_MipsCallSeqEnd,
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[SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
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// Select Condition Code
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def MipsSelectCC : SDNode<"MipsISD::SelectCC", SDT_MipsSelectCC>;
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// Conditional Move
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def MipsCMov : SDNode<"MipsISD::CMov", SDT_MipsCMov>;
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//===----------------------------------------------------------------------===//
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// Mips Instruction Predicate Definitions.
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//===----------------------------------------------------------------------===//
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def HasSEInReg : Predicate<"Subtarget.hasSEInReg()">;
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def HasBitCount : Predicate<"Subtarget.hasBitCount()">;
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def HasSwap : Predicate<"Subtarget.hasSwap()">;
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def HasCondMov : Predicate<"Subtarget.hasCondMov()">;
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//===----------------------------------------------------------------------===//
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// Mips Operand, Complex Patterns and Transformations Definitions.
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//===----------------------------------------------------------------------===//
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// Instruction operand types
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def brtarget : Operand<OtherVT>;
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def calltarget : Operand<i32>;
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def simm16 : Operand<i32>;
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def shamt : Operand<i32>;
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// Unsigned Operand
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def uimm16 : Operand<i32> {
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let PrintMethod = "printUnsignedImm";
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}
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// Address operand
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def mem : Operand<i32> {
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let PrintMethod = "printMemOperand";
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let MIOperandInfo = (ops simm16, CPURegs);
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}
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// Transformation Function - get the lower 16 bits.
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def LO16 : SDNodeXForm<imm, [{
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return getI32Imm((unsigned)N->getZExtValue() & 0xFFFF);
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}]>;
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// Transformation Function - get the higher 16 bits.
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def HI16 : SDNodeXForm<imm, [{
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return getI32Imm((unsigned)N->getZExtValue() >> 16);
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}]>;
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// Node immediate fits as 16-bit sign extended on target immediate.
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// e.g. addi, andi
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def immSExt16 : PatLeaf<(imm), [{
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if (N->getValueType(0) == MVT::i32)
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return (int32_t)N->getZExtValue() == (short)N->getZExtValue();
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else
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return (int64_t)N->getZExtValue() == (short)N->getZExtValue();
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}]>;
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// Node immediate fits as 16-bit zero extended on target immediate.
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// The LO16 param means that only the lower 16 bits of the node
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// immediate are caught.
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// e.g. addiu, sltiu
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def immZExt16 : PatLeaf<(imm), [{
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if (N->getValueType(0) == MVT::i32)
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return (uint32_t)N->getZExtValue() == (unsigned short)N->getZExtValue();
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else
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return (uint64_t)N->getZExtValue() == (unsigned short)N->getZExtValue();
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}], LO16>;
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// shamt field must fit in 5 bits.
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def immZExt5 : PatLeaf<(imm), [{
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return N->getZExtValue() == ((N->getZExtValue()) & 0x1f) ;
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}]>;
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// Mips Address Mode! SDNode frameindex could possibily be a match
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// since load and store instructions from stack used it.
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def addr : ComplexPattern<i32, 2, "SelectAddr", [frameindex], []>;
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//===----------------------------------------------------------------------===//
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// Instructions specific format
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//===----------------------------------------------------------------------===//
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// Arithmetic 3 register operands
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let isCommutable = 1 in
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class ArithR<bits<6> op, bits<6> func, string instr_asm, SDNode OpNode,
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InstrItinClass itin>:
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FR< op,
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func,
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(outs CPURegs:$dst),
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(ins CPURegs:$b, CPURegs:$c),
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!strconcat(instr_asm, "\t$dst, $b, $c"),
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[(set CPURegs:$dst, (OpNode CPURegs:$b, CPURegs:$c))], itin>;
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let isCommutable = 1 in
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class ArithOverflowR<bits<6> op, bits<6> func, string instr_asm>:
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FR< op,
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func,
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(outs CPURegs:$dst),
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(ins CPURegs:$b, CPURegs:$c),
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!strconcat(instr_asm, "\t$dst, $b, $c"),
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[], IIAlu>;
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// Arithmetic 2 register operands
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class ArithI<bits<6> op, string instr_asm, SDNode OpNode,
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Operand Od, PatLeaf imm_type> :
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FI< op,
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(outs CPURegs:$dst),
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(ins CPURegs:$b, Od:$c),
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!strconcat(instr_asm, "\t$dst, $b, $c"),
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[(set CPURegs:$dst, (OpNode CPURegs:$b, imm_type:$c))], IIAlu>;
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class ArithOverflowI<bits<6> op, string instr_asm, SDNode OpNode,
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Operand Od, PatLeaf imm_type> :
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FI< op,
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(outs CPURegs:$dst),
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(ins CPURegs:$b, Od:$c),
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!strconcat(instr_asm, "\t$dst, $b, $c"),
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[], IIAlu>;
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// Arithmetic Multiply ADD/SUB
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let rd=0 in
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class MArithR<bits<6> func, string instr_asm> :
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FR< 0x1c,
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func,
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(outs CPURegs:$rs),
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(ins CPURegs:$rt),
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!strconcat(instr_asm, "\t$rs, $rt"),
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[], IIImul>;
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// Logical
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class LogicR<bits<6> func, string instr_asm, SDNode OpNode>:
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FR< 0x00,
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func,
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(outs CPURegs:$dst),
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(ins CPURegs:$b, CPURegs:$c),
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!strconcat(instr_asm, "\t$dst, $b, $c"),
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[(set CPURegs:$dst, (OpNode CPURegs:$b, CPURegs:$c))], IIAlu>;
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class LogicI<bits<6> op, string instr_asm, SDNode OpNode>:
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FI< op,
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(outs CPURegs:$dst),
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(ins CPURegs:$b, uimm16:$c),
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!strconcat(instr_asm, "\t$dst, $b, $c"),
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[(set CPURegs:$dst, (OpNode CPURegs:$b, immZExt16:$c))], IIAlu>;
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class LogicNOR<bits<6> op, bits<6> func, string instr_asm>:
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FR< op,
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func,
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(outs CPURegs:$dst),
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(ins CPURegs:$b, CPURegs:$c),
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!strconcat(instr_asm, "\t$dst, $b, $c"),
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[(set CPURegs:$dst, (not (or CPURegs:$b, CPURegs:$c)))], IIAlu>;
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// Shifts
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let rt = 0 in
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class LogicR_shift_imm<bits<6> func, string instr_asm, SDNode OpNode>:
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FR< 0x00,
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func,
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(outs CPURegs:$dst),
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(ins CPURegs:$b, shamt:$c),
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!strconcat(instr_asm, "\t$dst, $b, $c"),
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[(set CPURegs:$dst, (OpNode CPURegs:$b, immZExt5:$c))], IIAlu>;
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class LogicR_shift_reg<bits<6> func, string instr_asm, SDNode OpNode>:
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FR< 0x00,
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func,
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(outs CPURegs:$dst),
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(ins CPURegs:$b, CPURegs:$c),
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!strconcat(instr_asm, "\t$dst, $b, $c"),
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[(set CPURegs:$dst, (OpNode CPURegs:$b, CPURegs:$c))], IIAlu>;
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// Load Upper Imediate
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class LoadUpper<bits<6> op, string instr_asm>:
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FI< op,
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(outs CPURegs:$dst),
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(ins uimm16:$imm),
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!strconcat(instr_asm, "\t$dst, $imm"),
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[], IIAlu>;
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// Memory Load/Store
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let canFoldAsLoad = 1, hasDelaySlot = 1 in
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class LoadM<bits<6> op, string instr_asm, PatFrag OpNode>:
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FI< op,
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(outs CPURegs:$dst),
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(ins mem:$addr),
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!strconcat(instr_asm, "\t$dst, $addr"),
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[(set CPURegs:$dst, (OpNode addr:$addr))], IILoad>;
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class StoreM<bits<6> op, string instr_asm, PatFrag OpNode>:
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FI< op,
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(outs),
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(ins CPURegs:$dst, mem:$addr),
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!strconcat(instr_asm, "\t$dst, $addr"),
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[(OpNode CPURegs:$dst, addr:$addr)], IIStore>;
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// Conditional Branch
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let isBranch = 1, isTerminator=1, hasDelaySlot = 1 in {
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class CBranch<bits<6> op, string instr_asm, PatFrag cond_op>:
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FI< op,
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(outs),
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(ins CPURegs:$a, CPURegs:$b, brtarget:$offset),
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!strconcat(instr_asm, "\t$a, $b, $offset"),
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[(brcond (cond_op CPURegs:$a, CPURegs:$b), bb:$offset)],
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IIBranch>;
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class CBranchZero<bits<6> op, string instr_asm, PatFrag cond_op>:
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FI< op,
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(outs),
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(ins CPURegs:$src, brtarget:$offset),
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!strconcat(instr_asm, "\t$src, $offset"),
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[(brcond (cond_op CPURegs:$src, 0), bb:$offset)],
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IIBranch>;
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}
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// SetCC
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class SetCC_R<bits<6> op, bits<6> func, string instr_asm,
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PatFrag cond_op>:
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FR< op,
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func,
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(outs CPURegs:$dst),
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(ins CPURegs:$b, CPURegs:$c),
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!strconcat(instr_asm, "\t$dst, $b, $c"),
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[(set CPURegs:$dst, (cond_op CPURegs:$b, CPURegs:$c))],
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IIAlu>;
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class SetCC_I<bits<6> op, string instr_asm, PatFrag cond_op,
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Operand Od, PatLeaf imm_type>:
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FI< op,
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(outs CPURegs:$dst),
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(ins CPURegs:$b, Od:$c),
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!strconcat(instr_asm, "\t$dst, $b, $c"),
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[(set CPURegs:$dst, (cond_op CPURegs:$b, imm_type:$c))],
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IIAlu>;
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// Unconditional branch
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let isBranch=1, isTerminator=1, isBarrier=1, hasDelaySlot = 1 in
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class JumpFJ<bits<6> op, string instr_asm>:
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FJ< op,
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(outs),
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(ins brtarget:$target),
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!strconcat(instr_asm, "\t$target"),
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[(br bb:$target)], IIBranch>;
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let isBranch=1, isTerminator=1, isBarrier=1, rd=0, hasDelaySlot = 1 in
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class JumpFR<bits<6> op, bits<6> func, string instr_asm>:
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FR< op,
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func,
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(outs),
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(ins CPURegs:$target),
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!strconcat(instr_asm, "\t$target"),
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[(brind CPURegs:$target)], IIBranch>;
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// Jump and Link (Call)
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let isCall=1, hasDelaySlot=1,
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// All calls clobber the non-callee saved registers...
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Defs = [AT, V0, V1, A0, A1, A2, A3, T0, T1, T2, T3, T4, T5, T6, T7, T8, T9,
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K0, K1, F0, F1, F2, F3, F4, F5, F6, F7, F8, F9, F10, F11, F12, F13,
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F14, F15, F16, F17, F18, F19], Uses = [GP] in {
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class JumpLink<bits<6> op, string instr_asm>:
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FJ< op,
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(outs),
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(ins calltarget:$target),
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!strconcat(instr_asm, "\t$target"),
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[(MipsJmpLink imm:$target)], IIBranch>;
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let rd=31 in
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class JumpLinkReg<bits<6> op, bits<6> func, string instr_asm>:
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FR< op,
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func,
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(outs),
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(ins CPURegs:$rs),
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!strconcat(instr_asm, "\t$rs"),
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[(MipsJmpLink CPURegs:$rs)], IIBranch>;
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class BranchLink<string instr_asm>:
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FI< 0x1,
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(outs),
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(ins CPURegs:$rs, brtarget:$target),
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!strconcat(instr_asm, "\t$rs, $target"),
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[], IIBranch>;
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}
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// Mul, Div
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class MulDiv<bits<6> func, string instr_asm, InstrItinClass itin>:
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FR< 0x00,
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func,
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(outs),
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(ins CPURegs:$a, CPURegs:$b),
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!strconcat(instr_asm, "\t$a, $b"),
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[], itin>;
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// Move from Hi/Lo
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class MoveFromLOHI<bits<6> func, string instr_asm>:
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FR< 0x00,
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func,
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(outs CPURegs:$dst),
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(ins),
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!strconcat(instr_asm, "\t$dst"),
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[], IIHiLo>;
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class MoveToLOHI<bits<6> func, string instr_asm>:
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FR< 0x00,
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func,
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(outs),
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(ins CPURegs:$src),
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!strconcat(instr_asm, "\t$src"),
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[], IIHiLo>;
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class EffectiveAddress<string instr_asm> :
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FI<0x09,
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(outs CPURegs:$dst),
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(ins mem:$addr),
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instr_asm,
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[(set CPURegs:$dst, addr:$addr)], IIAlu>;
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// Count Leading Ones/Zeros in Word
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class CountLeading<bits<6> func, string instr_asm, SDNode CountOp>:
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FR< 0x1c, func, (outs CPURegs:$dst), (ins CPURegs:$src),
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!strconcat(instr_asm, "\t$dst, $src"),
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[(set CPURegs:$dst, (CountOp CPURegs:$src))], IIAlu>;
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// Sign Extend in Register.
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class SignExtInReg<bits<6> func, string instr_asm, ValueType vt>:
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FR< 0x3f, func, (outs CPURegs:$dst), (ins CPURegs:$src),
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!strconcat(instr_asm, "\t$dst, $src"),
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[(set CPURegs:$dst, (sext_inreg CPURegs:$src, vt))], NoItinerary>;
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// Byte Swap
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class ByteSwap<bits<6> func, string instr_asm>:
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FR< 0x1f, func, (outs CPURegs:$dst), (ins CPURegs:$src),
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!strconcat(instr_asm, "\t$dst, $src"),
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[(set CPURegs:$dst, (bswap CPURegs:$src))], NoItinerary>;
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// Conditional Move
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class CondMov<bits<6> func, string instr_asm, PatLeaf MovCode>:
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FR< 0x00, func, (outs CPURegs:$dst), (ins CPURegs:$F, CPURegs:$T,
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CPURegs:$cond), !strconcat(instr_asm, "\t$dst, $T, $cond"),
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[(set CPURegs:$dst, (MipsCMov CPURegs:$F, CPURegs:$T,
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CPURegs:$cond, MovCode))], NoItinerary>;
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//===----------------------------------------------------------------------===//
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// Pseudo instructions
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//===----------------------------------------------------------------------===//
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// As stack alignment is always done with addiu, we need a 16-bit immediate
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let Defs = [SP], Uses = [SP] in {
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def ADJCALLSTACKDOWN : MipsPseudo<(outs), (ins uimm16:$amt),
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"!ADJCALLSTACKDOWN $amt",
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[(callseq_start timm:$amt)]>;
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def ADJCALLSTACKUP : MipsPseudo<(outs), (ins uimm16:$amt1, uimm16:$amt2),
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"!ADJCALLSTACKUP $amt1",
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[(callseq_end timm:$amt1, timm:$amt2)]>;
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}
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// Some assembly macros need to avoid pseudoinstructions and assembler
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// automatic reodering, we should reorder ourselves.
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def MACRO : MipsPseudo<(outs), (ins), ".set\tmacro", []>;
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def REORDER : MipsPseudo<(outs), (ins), ".set\treorder", []>;
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def NOMACRO : MipsPseudo<(outs), (ins), ".set\tnomacro", []>;
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def NOREORDER : MipsPseudo<(outs), (ins), ".set\tnoreorder", []>;
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// When handling PIC code the assembler needs .cpload and .cprestore
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// directives. If the real instructions corresponding these directives
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// are used, we have the same behavior, but get also a bunch of warnings
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// from the assembler.
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def CPLOAD : MipsPseudo<(outs), (ins CPURegs:$picreg), ".cpload\t$picreg", []>;
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def CPRESTORE : MipsPseudo<(outs), (ins uimm16:$loc), ".cprestore\t$loc\n", []>;
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// The supported Mips ISAs dont have any instruction close to the SELECT_CC
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// operation. The solution is to create a Mips pseudo SELECT_CC instruction
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// (MipsSelectCC), use LowerSELECT_CC to generate this instruction and finally
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// replace it for real supported nodes into EmitInstrWithCustomInserter
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let usesCustomDAGSchedInserter = 1 in {
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class PseudoSelCC<RegisterClass RC, string asmstr>:
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MipsPseudo<(outs RC:$dst), (ins CPURegs:$CmpRes, RC:$T, RC:$F), asmstr,
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[(set RC:$dst, (MipsSelectCC CPURegs:$CmpRes, RC:$T, RC:$F))]>;
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}
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def Select_CC : PseudoSelCC<CPURegs, "# MipsSelect_CC_i32">;
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//===----------------------------------------------------------------------===//
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// Instruction definition
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// MipsI Instructions
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//===----------------------------------------------------------------------===//
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/// Arithmetic Instructions (ALU Immediate)
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def ADDiu : ArithI<0x09, "addiu", add, simm16, immSExt16>;
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def ADDi : ArithOverflowI<0x08, "addi", add, simm16, immSExt16>;
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def SLTi : SetCC_I<0x0a, "slti", setlt, simm16, immSExt16>;
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def SLTiu : SetCC_I<0x0b, "sltiu", setult, simm16, immSExt16>;
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def ANDi : LogicI<0x0c, "andi", and>;
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def ORi : LogicI<0x0d, "ori", or>;
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def XORi : LogicI<0x0e, "xori", xor>;
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def LUi : LoadUpper<0x0f, "lui">;
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/// Arithmetic Instructions (3-Operand, R-Type)
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def ADDu : ArithR<0x00, 0x21, "addu", add, IIAlu>;
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def SUBu : ArithR<0x00, 0x23, "subu", sub, IIAlu>;
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def ADD : ArithOverflowR<0x00, 0x20, "add">;
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def SUB : ArithOverflowR<0x00, 0x22, "sub">;
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def SLT : SetCC_R<0x00, 0x2a, "slt", setlt>;
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def SLTu : SetCC_R<0x00, 0x2b, "sltu", setult>;
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def AND : LogicR<0x24, "and", and>;
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def OR : LogicR<0x25, "or", or>;
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def XOR : LogicR<0x26, "xor", xor>;
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def NOR : LogicNOR<0x00, 0x27, "nor">;
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/// Shift Instructions
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def SLL : LogicR_shift_imm<0x00, "sll", shl>;
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def SRL : LogicR_shift_imm<0x02, "srl", srl>;
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def SRA : LogicR_shift_imm<0x03, "sra", sra>;
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def SLLV : LogicR_shift_reg<0x04, "sllv", shl>;
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def SRLV : LogicR_shift_reg<0x06, "srlv", srl>;
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def SRAV : LogicR_shift_reg<0x07, "srav", sra>;
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/// Load and Store Instructions
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def LB : LoadM<0x20, "lb", sextloadi8>;
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def LBu : LoadM<0x24, "lbu", zextloadi8>;
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def LH : LoadM<0x21, "lh", sextloadi16>;
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def LHu : LoadM<0x25, "lhu", zextloadi16>;
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def LW : LoadM<0x23, "lw", load>;
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def SB : StoreM<0x28, "sb", truncstorei8>;
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def SH : StoreM<0x29, "sh", truncstorei16>;
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def SW : StoreM<0x2b, "sw", store>;
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/// Jump and Branch Instructions
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def J : JumpFJ<0x02, "j">;
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def JR : JumpFR<0x00, 0x08, "jr">;
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def JAL : JumpLink<0x03, "jal">;
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def JALR : JumpLinkReg<0x00, 0x09, "jalr">;
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def BEQ : CBranch<0x04, "beq", seteq>;
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def BNE : CBranch<0x05, "bne", setne>;
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let rt=1 in
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def BGEZ : CBranchZero<0x01, "bgez", setge>;
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let rt=0 in {
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def BGTZ : CBranchZero<0x07, "bgtz", setgt>;
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def BLEZ : CBranchZero<0x07, "blez", setle>;
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def BLTZ : CBranchZero<0x01, "bltz", setlt>;
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}
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def BGEZAL : BranchLink<"bgezal">;
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def BLTZAL : BranchLink<"bltzal">;
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let isReturn=1, isTerminator=1, hasDelaySlot=1,
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isBarrier=1, hasCtrlDep=1, rs=0, rt=0, shamt=0 in
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def RET : FR <0x00, 0x02, (outs), (ins CPURegs:$target),
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"jr\t$target", [(MipsRet CPURegs:$target)], IIBranch>;
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/// Multiply and Divide Instructions.
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let Defs = [HI, LO] in {
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def MULT : MulDiv<0x18, "mult", IIImul>;
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def MULTu : MulDiv<0x19, "multu", IIImul>;
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def DIV : MulDiv<0x1a, "div", IIIdiv>;
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def DIVu : MulDiv<0x1b, "divu", IIIdiv>;
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}
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let Defs = [HI] in
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def MTHI : MoveToLOHI<0x11, "mthi">;
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let Defs = [LO] in
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def MTLO : MoveToLOHI<0x13, "mtlo">;
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let Uses = [HI] in
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def MFHI : MoveFromLOHI<0x10, "mfhi">;
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let Uses = [LO] in
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def MFLO : MoveFromLOHI<0x12, "mflo">;
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/// Sign Ext In Register Instructions.
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let Predicates = [HasSEInReg] in {
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let shamt = 0x10, rs = 0 in
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def SEB : SignExtInReg<0x21, "seb", i8>;
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let shamt = 0x18, rs = 0 in
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def SEH : SignExtInReg<0x20, "seh", i16>;
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}
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/// Count Leading
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let Predicates = [HasBitCount] in {
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let rt = 0 in
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def CLZ : CountLeading<0b010110, "clz", ctlz>;
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}
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/// Byte Swap
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let Predicates = [HasSwap] in {
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let shamt = 0x3, rs = 0 in
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def WSBW : ByteSwap<0x20, "wsbw">;
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}
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/// Conditional Move
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def MIPS_CMOV_ZERO : PatLeaf<(i32 0)>;
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def MIPS_CMOV_NZERO : PatLeaf<(i32 1)>;
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let Predicates = [HasCondMov], isTwoAddress = 1 in {
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def MOVN : CondMov<0x0a, "movn", MIPS_CMOV_NZERO>;
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def MOVZ : CondMov<0x0b, "movz", MIPS_CMOV_ZERO>;
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}
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/// No operation
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let addr=0 in
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def NOP : FJ<0, (outs), (ins), "nop", [], IIAlu>;
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// FrameIndexes are legalized when they are operands from load/store
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// instructions. The same not happens for stack address copies, so an
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// add op with mem ComplexPattern is used and the stack address copy
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// can be matched. It's similar to Sparc LEA_ADDRi
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def LEA_ADDiu : EffectiveAddress<"addiu\t$dst, ${addr:stackloc}">;
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// MADD*/MSUB* are not part of MipsI either.
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//def MADD : MArithR<0x00, "madd">;
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//def MADDU : MArithR<0x01, "maddu">;
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//def MSUB : MArithR<0x04, "msub">;
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//def MSUBU : MArithR<0x05, "msubu">;
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// MUL is a assembly macro in the current used ISAs. In recent ISA's
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// it is a real instruction.
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//def MUL : ArithR<0x1c, 0x02, "mul", mul, IIImul>;
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//===----------------------------------------------------------------------===//
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// Arbitrary patterns that map to one or more instructions
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//===----------------------------------------------------------------------===//
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// Small immediates
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def : Pat<(i32 immSExt16:$in),
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(ADDiu ZERO, imm:$in)>;
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def : Pat<(i32 immZExt16:$in),
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(ORi ZERO, imm:$in)>;
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// Arbitrary immediates
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def : Pat<(i32 imm:$imm),
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(ORi (LUi (HI16 imm:$imm)), (LO16 imm:$imm))>;
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// Carry patterns
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def : Pat<(subc CPURegs:$lhs, CPURegs:$rhs),
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(SUBu CPURegs:$lhs, CPURegs:$rhs)>;
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def : Pat<(addc CPURegs:$lhs, CPURegs:$rhs),
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(ADDu CPURegs:$lhs, CPURegs:$rhs)>;
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def : Pat<(addc CPURegs:$src, imm:$imm),
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(ADDiu CPURegs:$src, imm:$imm)>;
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// Call
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def : Pat<(MipsJmpLink (i32 tglobaladdr:$dst)),
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(JAL tglobaladdr:$dst)>;
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def : Pat<(MipsJmpLink (i32 texternalsym:$dst)),
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(JAL texternalsym:$dst)>;
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def : Pat<(MipsJmpLink CPURegs:$dst),
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(JALR CPURegs:$dst)>;
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// hi/lo relocs
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def : Pat<(MipsHi tglobaladdr:$in), (LUi tglobaladdr:$in)>;
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def : Pat<(add CPURegs:$hi, (MipsLo tglobaladdr:$lo)),
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(ADDiu CPURegs:$hi, tglobaladdr:$lo)>;
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def : Pat<(MipsHi tjumptable:$in), (LUi tjumptable:$in)>;
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def : Pat<(add CPURegs:$hi, (MipsLo tjumptable:$lo)),
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(ADDiu CPURegs:$hi, tjumptable:$lo)>;
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def : Pat<(MipsHi tconstpool:$in), (LUi tconstpool:$in)>;
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def : Pat<(add CPURegs:$hi, (MipsLo tconstpool:$lo)),
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(ADDiu CPURegs:$hi, tconstpool:$lo)>;
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// gp_rel relocs
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def : Pat<(add CPURegs:$gp, (MipsGPRel tglobaladdr:$in)),
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(ADDiu CPURegs:$gp, tglobaladdr:$in)>;
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def : Pat<(add CPURegs:$gp, (MipsGPRel tconstpool:$in)),
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(ADDiu CPURegs:$gp, tconstpool:$in)>;
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// Mips does not have "not", so we expand our way
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def : Pat<(not CPURegs:$in),
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(NOR CPURegs:$in, ZERO)>;
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// extended load and stores
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def : Pat<(extloadi1 addr:$src), (LBu addr:$src)>;
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def : Pat<(extloadi8 addr:$src), (LBu addr:$src)>;
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def : Pat<(extloadi16 addr:$src), (LHu addr:$src)>;
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// peepholes
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def : Pat<(store (i32 0), addr:$dst), (SW ZERO, addr:$dst)>;
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// brcond patterns
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def : Pat<(brcond (setne CPURegs:$lhs, 0), bb:$dst),
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(BNE CPURegs:$lhs, ZERO, bb:$dst)>;
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def : Pat<(brcond (seteq CPURegs:$lhs, 0), bb:$dst),
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(BEQ CPURegs:$lhs, ZERO, bb:$dst)>;
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def : Pat<(brcond (setge CPURegs:$lhs, CPURegs:$rhs), bb:$dst),
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(BEQ (SLT CPURegs:$lhs, CPURegs:$rhs), ZERO, bb:$dst)>;
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def : Pat<(brcond (setuge CPURegs:$lhs, CPURegs:$rhs), bb:$dst),
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(BEQ (SLTu CPURegs:$lhs, CPURegs:$rhs), ZERO, bb:$dst)>;
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def : Pat<(brcond (setge CPURegs:$lhs, immSExt16:$rhs), bb:$dst),
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(BEQ (SLTi CPURegs:$lhs, immSExt16:$rhs), ZERO, bb:$dst)>;
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def : Pat<(brcond (setuge CPURegs:$lhs, immSExt16:$rhs), bb:$dst),
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(BEQ (SLTiu CPURegs:$lhs, immSExt16:$rhs), ZERO, bb:$dst)>;
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def : Pat<(brcond (setle CPURegs:$lhs, CPURegs:$rhs), bb:$dst),
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(BEQ (SLT CPURegs:$rhs, CPURegs:$lhs), ZERO, bb:$dst)>;
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def : Pat<(brcond (setule CPURegs:$lhs, CPURegs:$rhs), bb:$dst),
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(BEQ (SLTu CPURegs:$rhs, CPURegs:$lhs), ZERO, bb:$dst)>;
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def : Pat<(brcond CPURegs:$cond, bb:$dst),
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(BNE CPURegs:$cond, ZERO, bb:$dst)>;
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// select patterns
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def : Pat<(select (setge CPURegs:$lhs, CPURegs:$rhs), CPURegs:$T, CPURegs:$F),
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(MOVZ CPURegs:$F, CPURegs:$T, (SLT CPURegs:$lhs, CPURegs:$rhs))>;
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def : Pat<(select (setuge CPURegs:$lhs, CPURegs:$rhs), CPURegs:$T, CPURegs:$F),
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(MOVZ CPURegs:$F, CPURegs:$T, (SLTu CPURegs:$lhs, CPURegs:$rhs))>;
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def : Pat<(select (setge CPURegs:$lhs, immSExt16:$rhs), CPURegs:$T, CPURegs:$F),
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(MOVZ CPURegs:$F, CPURegs:$T, (SLTi CPURegs:$lhs, immSExt16:$rhs))>;
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def : Pat<(select (setuge CPURegs:$lh, immSExt16:$rh), CPURegs:$T, CPURegs:$F),
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(MOVZ CPURegs:$F, CPURegs:$T, (SLTiu CPURegs:$lh, immSExt16:$rh))>;
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def : Pat<(select (setle CPURegs:$lhs, CPURegs:$rhs), CPURegs:$T, CPURegs:$F),
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(MOVZ CPURegs:$F, CPURegs:$T, (SLT CPURegs:$rhs, CPURegs:$lhs))>;
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def : Pat<(select (setule CPURegs:$lhs, CPURegs:$rhs), CPURegs:$T, CPURegs:$F),
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(MOVZ CPURegs:$F, CPURegs:$T, (SLTu CPURegs:$rhs, CPURegs:$lhs))>;
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def : Pat<(select (seteq CPURegs:$lhs, CPURegs:$rhs), CPURegs:$T, CPURegs:$F),
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(MOVZ CPURegs:$F, CPURegs:$T, (XOR CPURegs:$lhs, CPURegs:$rhs))>;
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def : Pat<(select (setne CPURegs:$lhs, CPURegs:$rhs), CPURegs:$T, CPURegs:$F),
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(MOVN CPURegs:$F, CPURegs:$T, (XOR CPURegs:$lhs, CPURegs:$rhs))>;
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def : Pat<(select CPURegs:$cond, CPURegs:$T, CPURegs:$F),
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(MOVN CPURegs:$F, CPURegs:$T, CPURegs:$cond)>;
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// setcc patterns
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def : Pat<(seteq CPURegs:$lhs, CPURegs:$rhs),
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(SLTu (XOR CPURegs:$lhs, CPURegs:$rhs), 1)>;
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def : Pat<(setne CPURegs:$lhs, CPURegs:$rhs),
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(SLTu ZERO, (XOR CPURegs:$lhs, CPURegs:$rhs))>;
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def : Pat<(setle CPURegs:$lhs, CPURegs:$rhs),
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(XORi (SLT CPURegs:$rhs, CPURegs:$lhs), 1)>;
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def : Pat<(setule CPURegs:$lhs, CPURegs:$rhs),
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(XORi (SLTu CPURegs:$rhs, CPURegs:$lhs), 1)>;
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def : Pat<(setgt CPURegs:$lhs, CPURegs:$rhs),
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(SLT CPURegs:$rhs, CPURegs:$lhs)>;
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def : Pat<(setugt CPURegs:$lhs, CPURegs:$rhs),
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(SLTu CPURegs:$rhs, CPURegs:$lhs)>;
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def : Pat<(setge CPURegs:$lhs, CPURegs:$rhs),
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(XORi (SLT CPURegs:$lhs, CPURegs:$rhs), 1)>;
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def : Pat<(setuge CPURegs:$lhs, CPURegs:$rhs),
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(XORi (SLTu CPURegs:$lhs, CPURegs:$rhs), 1)>;
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def : Pat<(setge CPURegs:$lhs, immSExt16:$rhs),
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(XORi (SLTi CPURegs:$lhs, immSExt16:$rhs), 1)>;
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def : Pat<(setuge CPURegs:$lhs, immSExt16:$rhs),
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(XORi (SLTiu CPURegs:$lhs, immSExt16:$rhs), 1)>;
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//===----------------------------------------------------------------------===//
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// Floating Point Support
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//===----------------------------------------------------------------------===//
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include "MipsInstrFPU.td"
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