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f2c290dfa6
llvm-svn: 81545
25 lines
1.1 KiB
LLVM
25 lines
1.1 KiB
LLVM
; There should be exactly one vxor here.
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; RUN: llc < %s -march=ppc32 -mcpu=g5 --enable-unsafe-fp-math | \
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; RUN: grep vxor | count 1
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; There should be exactly one vsplti here.
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; RUN: llc < %s -march=ppc32 -mcpu=g5 --enable-unsafe-fp-math | \
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; RUN: grep vsplti | count 1
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define void @VXOR(<4 x float>* %P1, <4 x i32>* %P2, <4 x float>* %P3) {
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%tmp = load <4 x float>* %P3 ; <<4 x float>> [#uses=1]
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%tmp3 = load <4 x float>* %P1 ; <<4 x float>> [#uses=1]
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%tmp4 = fmul <4 x float> %tmp, %tmp3 ; <<4 x float>> [#uses=1]
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store <4 x float> %tmp4, <4 x float>* %P3
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store <4 x float> zeroinitializer, <4 x float>* %P1
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store <4 x i32> zeroinitializer, <4 x i32>* %P2
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ret void
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}
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define void @VSPLTI(<4 x i32>* %P2, <8 x i16>* %P3) {
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store <4 x i32> bitcast (<16 x i8> < i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1 > to <4 x i32>), <4 x i32>* %P2
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store <8 x i16> < i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1 >, <8 x i16>* %P3
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ret void
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}
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