Craig Topper 3d9d65f12a [X86] Run the AVX/AVX2 intrinsic tests in AVX512VL mode too just to make sure we don't break any older intrinsics. ... llvm-svn: 270183		2016-05-20 05:10:32 +00:00
..
AArch64	[ARM, AArch64] Match additional patterns to ldN instructions	2016-05-19 21:39:00 +00:00
AMDGPU	AMDGPU: Fix promote alloca for pointer loads	2016-05-18 23:20:24 +00:00
ARM	[ARM, AArch64] Match additional patterns to ldN instructions	2016-05-19 21:39:00 +00:00
BPF	[llc] New diagnostic handler	2016-05-16 14:28:02 +00:00
Generic	llc: Rework -run-pass option	2016-05-10 01:32:44 +00:00
Hexagon	When looking for a spill slot in reg scavenger, find one that matches RC	2016-05-18 18:16:00 +00:00
Inputs
Lanai
Mips	[mips][mips16] Fix ZERO is not a CPU16Regs register error from the machine verifier.	2016-05-19 10:42:14 +00:00
MIR	[llc] New diagnostic handler	2016-05-16 14:28:02 +00:00
MSP430
NVPTX	[NVPTX] Fix sign/zero-extending ldg/ldu instruction selection	2016-05-02 18:12:02 +00:00
PowerPC	Don't pass relocation-model= to tests that don't need it.	2016-05-18 00:27:17 +00:00
SPARC	[Sparc] Add Soft Float support	2016-05-18 09:14:13 +00:00
SystemZ	[SystemZ] Fix register ordering for BinaryRRF instructions	2016-05-18 13:24:57 +00:00
Thumb	ARM: stop emitting blx instructions for most calls on MachO.	2016-05-10 19:17:47 +00:00
Thumb2	ARM: stop emitting blx instructions for most calls on MachO.	2016-05-10 19:17:47 +00:00
WebAssembly	[WebAssembly] Make several CHECK lines less fragile using regexes and CHECK-DAG.	2016-05-19 01:52:56 +00:00
WinEH
X86	[X86] Run the AVX/AVX2 intrinsic tests in AVX512VL mode too just to make sure we don't break any older intrinsics.	2016-05-20 05:10:32 +00:00
XCore