Simon Atanasyan 4752b3e28d [mips] Fix lowering load/store instruction in PIC case ... If an operand of the `lw/sw` instructions is a symbol, these instructions incorrectly lowered using not-position-independent chain of commands. For PIC code we should use `lw/addiu` instructions with the `R_MIPS_GOT16` and `R_MIPS_LO16` relocations respectively. Instead of that LLVM generates position dependent code with the `R_MIPS_HI16` and `R_MIPS_LO16` relocations. This patch provides a fix for the bug by handling PIC case separately in the `MipsAsmParser::expandMemInst`. The main idea is to generate a chain of PIC instructions to load a symbol address into a register and then load the address content. The fix is not optimal and does not fix all PIC-related problems. This is a task for subsequent patches. Differential Revision: https://reviews.llvm.org/D65524 llvm-svn: 367580		2019-08-01 16:04:29 +00:00
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CMakeLists.txt
LLVMBuild.txt	Update the file headers across all of the LLVM projects in the monorepo	2019-01-19 08:50:56 +00:00
MipsAsmParser.cpp	[mips] Fix lowering load/store instruction in PIC case	2019-08-01 16:04:29 +00:00