Adam Nemet 78e81b5109 [DAGCombiner] Split up an indexed load if only the base pointer value is live ... Right now the load may not get DCE'd because of the side-effect of updating the base pointer. This can happen if we lower a read-modify-write of an illegal larger type (e.g. i48) such that the modification only affects one of the subparts (the lower i32 part but not the higher i16 part). See the testcase. In order to spot the dead load we need to revisit it when SimplifyDemandedBits decided that the value of the load is masked off. This is the CommitTargetLoweringOpt piece. I checked compile time with ARM64 by sending SPEC bitcode files through llc. No measurable change. Fixes <rdar://problem/16031651> llvm-svn: 208640		2014-05-12 23:00:03 +00:00
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AArch64	TableGen: use PrintMethods to print more aliases	2014-05-12 18:04:06 +00:00
ARM	Fix ARM bswap16.ll test on Windows	2014-05-12 22:13:07 +00:00
ARM64	[DAGCombiner] Split up an indexed load if only the base pointer value is live	2014-05-12 23:00:03 +00:00
CPP
Generic
Hexagon
Inputs
Mips	Allow sret on the second parameter as well as the first	2014-05-09 22:32:13 +00:00
MSP430
NVPTX
PowerPC	[PowerPC] Add global named register support	2014-05-11 19:29:11 +00:00
R600	R600: Add mul24 intrinsics	2014-05-12 17:49:57 +00:00
SPARC	Allow sret on the second parameter as well as the first	2014-05-09 22:32:13 +00:00
SystemZ
Thumb
Thumb2
X86	Try to fix an SDAG dependence issue with sret	2014-05-12 22:01:27 +00:00
XCore