Carl Ritson f3236bf71f [AMDGPU] Add v5f32/VReg_160 support for MIMG instructions ... Avoid having to round up to v8f32/VReg_256 when only 5 VGPRs are required for a MIMG address operand. Maintain _V8 instruction variants of pseudo instructions allowing assembly prior to GFX10 to work as-is. Currently the validator can tell for GFX10 what the correct size is, so will disallow oversize address registers. Reviewed By: rampitec Differential Revision: https://reviews.llvm.org/D103672		2021-06-08 11:11:40 +09:00
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AArch64	[llvm-mc][AArch64] HINT instruction disassembled as BTI	2021-05-14 10:05:37 +01:00
AMDGPU	[AMDGPU] Add v5f32/VReg_160 support for MIMG instructions	2021-06-08 11:11:40 +09:00
ARC
ARM	[ARM][disassembler] Fix incorrect number of MCOperands generated by the disassembler	2021-04-25 11:55:10 -07:00
Hexagon
Lanai
M68k	[M68k] Implement Disassembler	2021-04-19 22:24:12 +01:00
Mips
MSP430
PowerPC	[PowerPC] Add ROP Protection Instructions for PowerPC	2021-04-15 11:38:38 -05:00
RISCV
Sparc
SystemZ
WebAssembly	[WebAssembly] Update v128.any_true	2021-04-11 11:13:16 -07:00
X86
XCore