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4a69818916
This regards how mips16 is viewed. It's not really a target type but there has always been a target for it in the td files. It's more properly -mcpu=mips32 -mattr=+mips16 . This is how clang treats it but we have always had the -mcpu=mips16 which I probably should delete now but it will require updating all the .ll test cases for mips16. In this case it changed how we decide if we have a count bits instruction and whether instruction lowering should then expand ctlz. Now that we have dual mode compilation, -mattr=+mips16 really just indicates the inital processor mode that we are compiling for. (It is also possible to have -mcpu=64 -mattr=+mips16 but as far as I know, nobody has even built such a processor, though there is an architecture manual for this). llvm-svn: 188586
28 lines
889 B
LLVM
28 lines
889 B
LLVM
; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mcpu=mips32 -mattr=+mips16 -soft-float -mips16-hard-float -relocation-model=static < %s | FileCheck %s -check-prefix=static
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@x = global i32 28912, align 4
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@y = common global i32 0, align 4
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; Function Attrs: nounwind
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define i32 @main() #0 {
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entry:
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%retval = alloca i32, align 4
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store i32 0, i32* %retval
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%0 = load i32* @x, align 4
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%1 = call i32 @llvm.ctlz.i32(i32 %0, i1 true)
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store i32 %1, i32* @y, align 4
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ret i32 0
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}
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; static: .end main
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; Function Attrs: nounwind readnone
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declare i32 @llvm.ctlz.i32(i32, i1) #1
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attributes #0 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf"="true" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="true" }
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attributes #1 = { nounwind readnone }
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