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3e42041b2e
llvm-mirror/test/CodeGen/AArch64/GlobalISel
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Amara Emerson 3e42041b2e [AArch64][GlobalISel] Fall back during AArch64 isel if we have a volatile load. 
The tablegen imported patterns for sext(load(a)) don't check for single uses
of the load or delete the original after matching. As a result two loads are
left in the generated code. This particular issue will be fixed by adding
support for a G_SEXTLOAD opcode in future.

There are however other potential issues around this that wouldn't be fixed by
a G_SEXTLOAD, so until we have a proper solution we don't try to handle volatile
loads at all in the AArch64 selector.

Fixes/works around PR36018.

llvm-svn: 323371
2018-01-24 20:35:37 +00:00
..
arm64-callingconv-ios.ll MIR: Print the register class or bank in vreg defs 2017-10-24 18:04:54 +00:00
arm64-callingconv.ll MIR: Print the register class or bank in vreg defs 2017-10-24 18:04:54 +00:00
arm64-fallback.ll [CodeGen] Print RegClasses on MI in verbose mode 2018-01-18 17:59:06 +00:00
arm64-irtranslator-stackprotect.ll MIR: Print the register class or bank in vreg defs 2017-10-24 18:04:54 +00:00
arm64-irtranslator.ll Remove alignment argument from memcpy/memmove/memset in favour of alignment attributes (Step 1) 2018-01-19 17:13:12 +00:00
arm64-regbankselect.mir [AArch64] Map G_LOAD on FPR when the definition goes to a copy to FPR 2017-11-18 04:28:59 +00:00
call-translator-ios.ll MIR: Print the register class or bank in vreg defs 2017-10-24 18:04:54 +00:00
call-translator.ll MIR: Print the register class or bank in vreg defs 2017-10-24 18:04:54 +00:00
combine-anyext-crash.mir [GlobalISel] Fix legalizer trying to process a deleted instruction. 2017-10-06 19:24:15 +00:00
debug-insts.ll [CodeGen] Always use printReg to print registers in both MIR and debug 2017-11-30 16:12:24 +00:00
dynamic-alloca.ll MIR: Print the register class or bank in vreg defs 2017-10-24 18:04:54 +00:00
fallback-nofastisel.ll [GlobalISel] Don't fall back to FastISel. 2018-01-24 19:59:29 +00:00
fp128-legalize-crash-pr35690.mir [GlobalISel][Legalizer] Fix crash when trying to lower G_FNEG of fp128 types. 2017-12-19 17:21:35 +00:00
gisel-abort.ll
gisel-commandline-option.ll Fix the failure caused by r322773 2018-01-18 01:10:30 +00:00
gisel-fail-intermediate-legalizer.ll [GlobalISel]: Fix bug where we can report GISelFailure on erased instructions 2017-04-07 21:49:30 +00:00
inline-asm.ll GlobalISel: support trivial inlineasm calls. 2017-03-09 23:36:26 +00:00
irtranslator-bitcast.ll MIR: Print the register class or bank in vreg defs 2017-10-24 18:04:54 +00:00
irtranslator-exceptions.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
irtranslator-volatile-load-pr36018.ll [AArch64][GlobalISel] Fall back during AArch64 isel if we have a volatile load. 2018-01-24 20:35:37 +00:00
legalize-add.mir [GISel]: Rework legalization algorithm for better elimination of 2017-11-14 22:42:19 +00:00
legalize-and.mir [GISel]: Rework legalization algorithm for better elimination of 2017-11-14 22:42:19 +00:00
legalize-atomicrmw.mir [aarch64][globalisel] Add missing tests from r319216 2017-11-28 20:27:59 +00:00
legalize-cmp.mir [GISel]: Rework legalization algorithm for better elimination of 2017-11-14 22:42:19 +00:00
legalize-cmpxchg-with-success.mir [aarch64][globalisel] Legalize G_ATOMIC_CMPXCHG_WITH_SUCCESS and G_ATOMICRMW_* 2017-11-30 20:11:42 +00:00
legalize-cmpxchg.mir [aarch64][globalisel] Add missing tests from r319216 2017-11-28 20:27:59 +00:00
legalize-combines.mir GlobalISel: Enable the legalization of G_MERGE_VALUES and G_UNMERGE_VALUES 2017-12-01 08:19:10 +00:00
legalize-constant.mir [GISel]: Rework legalization algorithm for better elimination of 2017-11-14 22:42:19 +00:00
legalize-div.mir [GISel]: Rework legalization algorithm for better elimination of 2017-11-14 22:42:19 +00:00
legalize-exceptions.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
legalize-ext.mir [GISel]: Rework legalization algorithm for better elimination of 2017-11-14 22:42:19 +00:00
legalize-extracts.mir [GISel]: Rework legalization algorithm for better elimination of 2017-11-14 22:42:19 +00:00
legalize-fcmp.mir [GISel]: Rework legalization algorithm for better elimination of 2017-11-14 22:42:19 +00:00
legalize-fneg.mir MIR: Print the register class or bank in vreg defs 2017-10-24 18:04:54 +00:00
legalize-fptoi.mir [GISel]: Rework legalization algorithm for better elimination of 2017-11-14 22:42:19 +00:00
legalize-gep.mir MIR: Print the register class or bank in vreg defs 2017-10-24 18:04:54 +00:00
legalize-ignore-non-generic.mir MIR: Print the register class or bank in vreg defs 2017-10-24 18:04:54 +00:00
legalize-inserts.mir [GISel]: Rework legalization algorithm for better elimination of 2017-11-14 22:42:19 +00:00
legalize-itofp.mir [GISel]: Rework legalization algorithm for better elimination of 2017-11-14 22:42:19 +00:00
legalize-load-store.mir [GISel]: Rework legalization algorithm for better elimination of 2017-11-14 22:42:19 +00:00
legalize-merge-values.mir GlobalISel: Enable the legalization of G_MERGE_VALUES and G_UNMERGE_VALUES 2017-12-01 08:19:10 +00:00
legalize-mul.mir [GlobalISel][Legalizer] Fix legalization of llvm.smul.with.overflow 2018-01-03 04:56:56 +00:00
legalize-nonpowerof2eltsvec.mir GlobalISel: Enable the legalization of G_MERGE_VALUES and G_UNMERGE_VALUES 2017-12-01 08:19:10 +00:00
legalize-or.mir [GISel]: Rework legalization algorithm for better elimination of 2017-11-14 22:42:19 +00:00
legalize-phi.mir [GISel]: Rework legalization algorithm for better elimination of 2017-11-14 22:42:19 +00:00
legalize-pow.mir [MIR] Repurposing '$' sigil used by external symbols. Replacing with '&'. 2018-01-10 00:56:48 +00:00
legalize-property.mir
legalize-rem.mir [MIR] Repurposing '$' sigil used by external symbols. Replacing with '&'. 2018-01-10 00:56:48 +00:00
legalize-shift.mir [GISel]: Rework legalization algorithm for better elimination of 2017-11-14 22:42:19 +00:00
legalize-simple.mir [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
legalize-sub.mir [GISel]: Rework legalization algorithm for better elimination of 2017-11-14 22:42:19 +00:00
legalize-undef.mir [GISel]: Rework legalization algorithm for better elimination of 2017-11-14 22:42:19 +00:00
legalize-unmerge-values.mir GlobalISel: Enable the legalization of G_MERGE_VALUES and G_UNMERGE_VALUES 2017-12-01 08:19:10 +00:00
legalize-vaarg.mir [GISel]: Rework legalization algorithm for better elimination of 2017-11-14 22:42:19 +00:00
legalize-xor.mir [GISel]: Rework legalization algorithm for better elimination of 2017-11-14 22:42:19 +00:00
lit.local.cfg
localizer-in-O0-pipeline.mir [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
localizer.mir MIR: Print the register class or bank in vreg defs 2017-10-24 18:04:54 +00:00
machine-cse-mid-pipeline.mir GlobalISel: Make MachineCSE runnable in the middle of the GlobalISel 2018-01-18 02:06:56 +00:00
no-regclass.mir GlobalISel: Enable the legalization of G_MERGE_VALUES and G_UNMERGE_VALUES 2017-12-01 08:19:10 +00:00
reg-bank-128bit.mir [GISel][AArch64]: Fix illegal Generic copies in tests 2017-10-23 22:53:04 +00:00
regbankselect-dbg-value.mir [CodeGen] Always use printReg to print registers in both MIR and debug 2017-11-30 16:12:24 +00:00
regbankselect-default.mir MIR: Print the register class or bank in vreg defs 2017-10-24 18:04:54 +00:00
regbankselect-reg_sequence.mir [RegBankSelect] Support REG_SEQUENCE for generic mapping 2017-04-01 01:26:14 +00:00
select-atomicrmw.mir [globalisel][tablegen] Add support for importing G_ATOMIC_CMPXCHG, G_ATOMICRMW_* rules from SelectionDAG. 2017-11-28 22:07:05 +00:00
select-binop.mir MIR: Print the register class or bank in vreg defs 2017-10-24 18:04:54 +00:00
select-bitcast-bigendian.mir [GISel]: Remove redundant copies at the end of ISel 2018-01-24 01:35:26 +00:00
select-bitcast.mir [GISel]: Remove redundant copies at the end of ISel 2018-01-24 01:35:26 +00:00
select-br.mir [GISel]: Remove redundant copies at the end of ISel 2018-01-24 01:35:26 +00:00
select-bswap.mir MIR: Print the register class or bank in vreg defs 2017-10-24 18:04:54 +00:00
select-cbz.mir MIR: Print the register class or bank in vreg defs 2017-10-24 18:04:54 +00:00
select-cmpxchg.mir [globalisel][tablegen] Add support for importing G_ATOMIC_CMPXCHG, G_ATOMICRMW_* rules from SelectionDAG. 2017-11-28 22:07:05 +00:00
select-constant.mir MIR: Print the register class or bank in vreg defs 2017-10-24 18:04:54 +00:00
select-dbg-value.mir [CodeGen] Always use printReg to print registers in both MIR and debug 2017-11-30 16:12:24 +00:00
select-fma.mir MIR: Print the register class or bank in vreg defs 2017-10-24 18:04:54 +00:00
select-fp-casts.mir MIR: Print the register class or bank in vreg defs 2017-10-24 18:04:54 +00:00
select-gv-cmodel-large.mir [AArch64][GlobalISel] Add isel support for global values in the large code model. 2018-01-18 19:21:27 +00:00
select-imm.mir MIR: Print the register class or bank in vreg defs 2017-10-24 18:04:54 +00:00
select-implicit-def.mir MIR: Print the register class or bank in vreg defs 2017-10-24 18:04:54 +00:00
select-insert-extract.mir [MIRPrinter] Use %subreg.xxx syntax for subregister index operands 2017-11-06 21:46:06 +00:00
select-int-ext.mir [GISel]: Remove redundant copies at the end of ISel 2018-01-24 01:35:26 +00:00
select-int-ptr-casts.mir [GISel]: Remove redundant copies at the end of ISel 2018-01-24 01:35:26 +00:00
select-intrinsic-aarch64-hint.mir [globalisel] Add support for intrinsic_void 2017-09-19 13:23:01 +00:00
select-intrinsic-aarch64-sdiv.mir MIR: Print the register class or bank in vreg defs 2017-10-24 18:04:54 +00:00
select-intrinsic-crypto-aesmc.mir [globalisel][tablegen] Add support for multi-insn emission 2017-11-01 19:57:57 +00:00
select-load.mir [globalisel][tablegen] Add support for extload. 2017-11-13 18:30:23 +00:00
select-mul.mir [GlobalISel][TableGen] Add support for SDNodeXForm 2018-01-16 18:44:05 +00:00
select-muladd.mir MIR: Print the register class or bank in vreg defs 2017-10-24 18:04:54 +00:00
select-neon-vcvtfxu2fp.mir MIR: Print the register class or bank in vreg defs 2017-10-24 18:04:54 +00:00
select-phi.mir MIR: Print the register class or bank in vreg defs 2017-10-24 18:04:54 +00:00
select-pr32733.mir MIR: Print the register class or bank in vreg defs 2017-10-24 18:04:54 +00:00
select-property.mir [GlobalISel][AArch64] Split out select tests. NFC. 2017-03-15 16:29:37 +00:00
select-store.mir [GISel]: Remove redundant copies at the end of ISel 2018-01-24 01:35:26 +00:00
select-trunc.mir [GISel]: Remove redundant copies at the end of ISel 2018-01-24 01:35:26 +00:00
select-xor.mir MIR: Print the register class or bank in vreg defs 2017-10-24 18:04:54 +00:00
select.mir [GISel]: Remove redundant copies at the end of ISel 2018-01-24 01:35:26 +00:00
translate-gep.ll [GISel]: Don't create G_MUL with 1 during translation of GEP 2018-01-05 02:56:28 +00:00
unknown-intrinsic.ll [AArch64][GlobalISel] Fix assert fail with unknown intrinsic. 2018-01-02 18:56:39 +00:00
varargs-ios-translator.ll MIR: Print the register class or bank in vreg defs 2017-10-24 18:04:54 +00:00
vastart.ll MIR: Print the register class or bank in vreg defs 2017-10-24 18:04:54 +00:00
verify-regbankselected.mir [CodeGen] Use MachineOperand::print in the MIRPrinter for MO_Register. 2017-12-07 10:40:31 +00:00
verify-selected.mir [CodeGen] Use MachineOperand::print in the MIRPrinter for MO_Register. 2017-12-07 10:40:31 +00:00