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8e51f27003
artifacts along with DCE
Legalization Artifacts are all those insts that are there to make the
type system happy. Currently, the target needs to say all combinations
of extends and truncs are legal and there's no way of verifying that
post legalization, we only have *truly* legal instructions. This patch
changes roughly the legalization algorithm to process all illegal insts
at one go, and then process all truncs/extends that were added to
satisfy the type constraints separately trying to combine trivial cases
until they converge. This has the added benefit that, the target
legalizerinfo can only say which truncs and extends are okay and the
artifact combiner would combine away other exts and truncs.
Updated legalization algorithm to roughly the following pseudo code.
WorkList Insts, Artifacts;
collect_all_insts_and_artifacts(Insts, Artifacts);
do {
for (Inst in Insts)
legalizeInstrStep(Inst, Insts, Artifacts);
for (Artifact in Artifacts)
tryCombineArtifact(Artifact, Insts, Artifacts);
} while(!Insts.empty());
Also, wrote a simple wrapper equivalent to SetVector, except for
erasing, it avoids moving all elements over by one and instead just
nulls them out.
llvm-svn: 318210
190 lines
5.7 KiB
YAML
190 lines
5.7 KiB
YAML
# NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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# RUN: llc -O0 -run-pass=legalizer -global-isel %s -o - | FileCheck %s
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--- |
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target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
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target triple = "aarch64--"
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define void @test_scalar_add_big() {
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entry:
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ret void
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}
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define void @test_scalar_add_big_nonpow2() {
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entry:
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ret void
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}
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define void @test_scalar_add_small() {
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entry:
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ret void
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}
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define void @test_vector_add() {
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entry:
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ret void
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}
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define void @test_vector_add_nonpow2() {
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entry:
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ret void
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}
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...
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---
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name: test_scalar_add_big
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body: |
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bb.0.entry:
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liveins: %x0, %x1, %x2, %x3
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; CHECK-LABEL: name: test_scalar_add_big
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; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY %x0
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; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY %x1
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; CHECK: [[COPY2:%[0-9]+]]:_(s64) = COPY %x2
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; CHECK: [[COPY3:%[0-9]+]]:_(s64) = COPY %x3
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; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
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; CHECK: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[C]](s32)
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; CHECK: [[UADDE:%[0-9]+]]:_(s64), [[UADDE1:%[0-9]+]]:_(s1) = G_UADDE [[COPY]], [[COPY2]], [[TRUNC]]
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; CHECK: [[UADDE2:%[0-9]+]]:_(s64), [[UADDE3:%[0-9]+]]:_(s1) = G_UADDE [[COPY1]], [[COPY3]], [[UADDE1]]
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; CHECK: %x0 = COPY [[UADDE]](s64)
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; CHECK: %x1 = COPY [[UADDE2]](s64)
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%0:_(s64) = COPY %x0
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%1:_(s64) = COPY %x1
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%2:_(s64) = COPY %x2
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%3:_(s64) = COPY %x3
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%4:_(s128) = G_MERGE_VALUES %0, %1
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%5:_(s128) = G_MERGE_VALUES %2, %3
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%6:_(s128) = G_ADD %4, %5
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%7:_(s64), %8:_(s64) = G_UNMERGE_VALUES %6
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%x0 = COPY %7
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%x1 = COPY %8
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...
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---
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name: test_scalar_add_big_nonpow2
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registers:
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- { id: 0, class: _ }
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- { id: 1, class: _ }
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- { id: 2, class: _ }
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- { id: 3, class: _ }
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- { id: 4, class: _ }
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- { id: 5, class: _ }
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- { id: 6, class: _ }
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- { id: 7, class: _ }
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- { id: 8, class: _ }
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- { id: 9, class: _ }
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body: |
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bb.0.entry:
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liveins: %x0, %x1, %x2, %x3
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; CHECK-LABEL: name: test_scalar_add_big_nonpow2
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; CHECK-NOT: G_MERGE_VALUES
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; CHECK-NOT: G_UNMERGE_VALUES
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; CHECK-DAG: [[CARRY0_32:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
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; CHECK-DAG: [[CARRY0:%[0-9]+]]:_(s1) = G_TRUNC [[CARRY0_32]]
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; CHECK: [[RES_LO:%[0-9]+]]:_(s64), [[CARRY1:%[0-9]+]]:_(s1) = G_UADDE %0, %1, [[CARRY0]]
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; CHECK: [[RES_MI:%[0-9]+]]:_(s64), [[CARRY2:%[0-9]+]]:_(s1) = G_UADDE %1, %2, [[CARRY1]]
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; CHECK: [[RES_HI:%[0-9]+]]:_(s64), {{%.*}}(s1) = G_UADDE %2, %3, [[CARRY2]]
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; CHECK-NOT: G_MERGE_VALUES
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; CHECK-NOT: G_UNMERGE_VALUES
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; CHECK: %x0 = COPY [[RES_LO]]
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; CHECK: %x1 = COPY [[RES_MI]]
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; CHECK: %x2 = COPY [[RES_HI]]
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%0(s64) = COPY %x0
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%1(s64) = COPY %x1
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%2(s64) = COPY %x2
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%3(s64) = COPY %x3
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%4(s192) = G_MERGE_VALUES %0, %1, %2
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%5(s192) = G_MERGE_VALUES %1, %2, %3
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%6(s192) = G_ADD %4, %5
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%7(s64), %8(s64), %9(s64) = G_UNMERGE_VALUES %6
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%x0 = COPY %7
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%x1 = COPY %8
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%x2 = COPY %9
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...
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---
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name: test_scalar_add_small
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body: |
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bb.0.entry:
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liveins: %x0, %x1, %x2, %x3
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; CHECK-LABEL: name: test_scalar_add_small
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; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY %x0
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; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY %x1
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; CHECK: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
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; CHECK: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)
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; CHECK: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[TRUNC]], [[TRUNC1]]
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; CHECK: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[ADD]](s32)
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; CHECK: %x0 = COPY [[ANYEXT]](s64)
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%0:_(s64) = COPY %x0
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%1:_(s64) = COPY %x1
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%2:_(s8) = G_TRUNC %0
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%3:_(s8) = G_TRUNC %1
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%4:_(s8) = G_ADD %2, %3
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%5:_(s64) = G_ANYEXT %4
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%x0 = COPY %5
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...
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---
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name: test_vector_add
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body: |
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bb.0.entry:
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liveins: %q0, %q1, %q2, %q3
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; CHECK-LABEL: name: test_vector_add
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; CHECK: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY %q0
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; CHECK: [[COPY1:%[0-9]+]]:_(<2 x s64>) = COPY %q1
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; CHECK: [[COPY2:%[0-9]+]]:_(<2 x s64>) = COPY %q2
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; CHECK: [[COPY3:%[0-9]+]]:_(<2 x s64>) = COPY %q3
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; CHECK: [[ADD:%[0-9]+]]:_(<2 x s64>) = G_ADD [[COPY]], [[COPY2]]
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; CHECK: [[ADD1:%[0-9]+]]:_(<2 x s64>) = G_ADD [[COPY1]], [[COPY3]]
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; CHECK: %q0 = COPY [[ADD]](<2 x s64>)
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; CHECK: %q1 = COPY [[ADD1]](<2 x s64>)
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%0:_(<2 x s64>) = COPY %q0
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%1:_(<2 x s64>) = COPY %q1
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%2:_(<2 x s64>) = COPY %q2
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%3:_(<2 x s64>) = COPY %q3
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%4:_(<4 x s64>) = G_MERGE_VALUES %0, %1
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%5:_(<4 x s64>) = G_MERGE_VALUES %2, %3
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%6:_(<4 x s64>) = G_ADD %4, %5
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%7:_(<2 x s64>), %8:_(<2 x s64>) = G_UNMERGE_VALUES %6
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%q0 = COPY %7
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%q1 = COPY %8
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...
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---
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name: test_vector_add_nonpow2
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registers:
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- { id: 0, class: _ }
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- { id: 1, class: _ }
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- { id: 2, class: _ }
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- { id: 3, class: _ }
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- { id: 4, class: _ }
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- { id: 5, class: _ }
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- { id: 6, class: _ }
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- { id: 7, class: _ }
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- { id: 8, class: _ }
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- { id: 9, class: _ }
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body: |
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bb.0.entry:
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liveins: %q0, %q1, %q2, %q3
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; CHECK-LABEL: name: test_vector_add_nonpow2
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; CHECK-NOT: G_EXTRACT
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; CHECK-NOT: G_SEQUENCE
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; CHECK: [[RES_LO:%[0-9]+]]:_(<2 x s64>) = G_ADD %0, %1
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; CHECK: [[RES_MI:%[0-9]+]]:_(<2 x s64>) = G_ADD %1, %2
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; CHECK: [[RES_HI:%[0-9]+]]:_(<2 x s64>) = G_ADD %2, %3
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; CHECK-NOT: G_EXTRACT
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; CHECK-NOT: G_SEQUENCE
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; CHECK: %q0 = COPY [[RES_LO]]
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; CHECK: %q1 = COPY [[RES_MI]]
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; CHECK: %q2 = COPY [[RES_HI]]
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%0(<2 x s64>) = COPY %q0
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%1(<2 x s64>) = COPY %q1
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%2(<2 x s64>) = COPY %q2
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%3(<2 x s64>) = COPY %q3
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%4(<6 x s64>) = G_MERGE_VALUES %0, %1, %2
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%5(<6 x s64>) = G_MERGE_VALUES %1, %2, %3
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%6(<6 x s64>) = G_ADD %4, %5
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%7(<2 x s64>), %8(<2 x s64>), %9(<2 x s64>) = G_UNMERGE_VALUES %6
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%q0 = COPY %7
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%q1 = COPY %8
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%q2 = COPY %9
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...
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