1
0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-11-23 19:23:23 +01:00
llvm-mirror/test/CodeGen/AArch64/GlobalISel/select-br.mir
Aditya Nandakumar 8339b2bebd [GISel]: Remove redundant copies at the end of ISel
https://reviews.llvm.org/D42402

A lot of these copies are useless (copies b/w VRegs having the same
regclass) and should be cleaned up.

llvm-svn: 323291
2018-01-24 01:35:26 +00:00

74 lines
1.3 KiB
YAML

# RUN: llc -mtriple=aarch64-- -run-pass=instruction-select -verify-machineinstrs -global-isel %s -o - | FileCheck %s
--- |
target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
define void @unconditional_br() { ret void }
define void @conditional_br() { ret void }
define void @indirect_br() { ret void }
...
---
# CHECK-LABEL: name: unconditional_br
name: unconditional_br
legalized: true
regBankSelected: true
# CHECK: body:
# CHECK: bb.0:
# CHECK: successors: %bb.0
# CHECK: B %bb.0
body: |
bb.0:
successors: %bb.0
G_BR %bb.0
...
---
# CHECK-LABEL: name: conditional_br
name: conditional_br
legalized: true
regBankSelected: true
registers:
- { id: 0, class: gpr }
- { id: 1, class: gpr }
# CHECK: body:
# CHECK: bb.0:
# CHECK: TBNZW %1, 0, %bb.1
# CHECK: B %bb.0
body: |
bb.0:
successors: %bb.0, %bb.1
%1(s32) = COPY %w0
%0(s1) = G_TRUNC %1
G_BRCOND %0(s1), %bb.1
G_BR %bb.0
bb.1:
...
---
# CHECK-LABEL: name: indirect_br
name: indirect_br
legalized: true
regBankSelected: true
registers:
- { id: 0, class: gpr }
# CHECK: body:
# CHECK: bb.0:
# CHECK: %0:gpr64 = COPY %x0
# CHECK: BR %0
body: |
bb.0:
successors: %bb.0, %bb.1
%0(p0) = COPY %x0
G_BRINDIRECT %0(p0)
bb.1:
...