Matt Arsenault 3e43a6c1b7 TableGen: Add MinAlignment predicate ... AMDGPU uses some custom code predicates for testing alignments. I'm still having trouble comprehending the behavior of predicate bits in the PatFrag hierarchy. Any attempt to abstract these properties unexpectdly fails to apply them. llvm-svn: 367373		2019-07-31 00:14:43 +00:00
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GlobalISel	GlobalISel: Add G_ATOMICRMW_{FADD|FSUB}	2019-07-30 23:56:30 +00:00
CodeGenCWrappers.h	Update the file headers across all of the LLVM projects in the monorepo	2019-01-19 08:50:56 +00:00
GenericOpcodes.td	GlobalISel: Add G_ATOMICRMW_{FADD|FSUB}	2019-07-30 23:56:30 +00:00
Target.td	[AMDGPU] Allow register tuples to set asm names	2019-07-19 18:05:01 +00:00
TargetCallingConv.td	DAG: propagate whether an arg is a pointer for CallingConv decisions.	2019-04-15 12:03:54 +00:00
TargetInstrPredicate.td	Update the file headers across all of the LLVM projects in the monorepo	2019-01-19 08:50:56 +00:00
TargetIntrinsicInfo.h	Update the file headers across all of the LLVM projects in the monorepo	2019-01-19 08:50:56 +00:00
TargetItinerary.td	Update the file headers across all of the LLVM projects in the monorepo	2019-01-19 08:50:56 +00:00
TargetLoweringObjectFile.h	[AsmPrinter] Make the encoding of call sites in .gcc_except_table configurable and use for RISC-V	2019-07-17 14:00:35 +00:00
TargetMachine.h	[TargetMachine] error message unsupported code model	2019-05-22 10:40:26 +00:00
TargetOptions.h	[TargetOption] Add option to ebanble the debug entry values	2019-06-26 08:35:43 +00:00
TargetPfmCounters.td	Update the file headers across all of the LLVM projects in the monorepo	2019-01-19 08:50:56 +00:00
TargetSchedule.td	Fix typos: (re)?sor?uce -> (re)?source	2019-04-26 05:56:23 +00:00
TargetSelectionDAG.td	TableGen: Add MinAlignment predicate	2019-07-31 00:14:43 +00:00