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13 lines
396 B
LLVM
13 lines
396 B
LLVM
; RUN: llc -march=hexagon -disable-hexagon-misched < %s | FileCheck %s
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; Check that we generate dual stores in one packet in V4
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; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#{{[0-9]+}}){{ *}}=
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; CHECK-NEXT: memw(r{{[0-9]+}}{{ *}}+{{ *}}#{{[0-9]+}}){{ *}}=
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define i32 @main(i32 %v, i32* %p1, i32* %p2) nounwind {
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entry:
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store i32 %v, i32* %p1, align 4
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store i32 %v, i32* %p2, align 4
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ret i32 0
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}
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