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d2b344c685
when run on an Intel Atom processor. The failures have arisen due to changes elsewhere in the trunk over the past 8 weeks or so. These failures were not detected by the Atom buildbot because the CPU on the Atom buildbot was not being detected as an Atom CPU. The fix for this problem is in Host.cpp and X86Subtarget.cpp, but shall remain commented out until the current set of Atom test failures are fixed. Patch by Andy Zhang and Tyler Nowicki! llvm-svn: 160451
57 lines
1.6 KiB
LLVM
57 lines
1.6 KiB
LLVM
; RUN: llc < %s -march=x86 -mattr=+sse2 | FileCheck %s
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; When loading the shift amount from memory, avoid generating the splat.
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define void @shift5a(<4 x i32> %val, <4 x i32>* %dst, i32* %pamt) nounwind {
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entry:
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; CHECK: shift5a:
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; CHECK: movd
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; CHECK: pslld
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%amt = load i32* %pamt
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%tmp0 = insertelement <4 x i32> undef, i32 %amt, i32 0
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%shamt = shufflevector <4 x i32> %tmp0, <4 x i32> undef, <4 x i32> zeroinitializer
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%shl = shl <4 x i32> %val, %shamt
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store <4 x i32> %shl, <4 x i32>* %dst
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ret void
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}
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define void @shift5b(<4 x i32> %val, <4 x i32>* %dst, i32* %pamt) nounwind {
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entry:
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; CHECK: shift5b:
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; CHECK: movd
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; CHECK: psrad
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%amt = load i32* %pamt
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%tmp0 = insertelement <4 x i32> undef, i32 %amt, i32 0
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%shamt = shufflevector <4 x i32> %tmp0, <4 x i32> undef, <4 x i32> zeroinitializer
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%shr = ashr <4 x i32> %val, %shamt
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store <4 x i32> %shr, <4 x i32>* %dst
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ret void
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}
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define void @shift5c(<4 x i32> %val, <4 x i32>* %dst, i32 %amt) nounwind {
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entry:
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; CHECK: shift5c:
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; CHECK: movd
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; CHECK: pslld
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%tmp0 = insertelement <4 x i32> undef, i32 %amt, i32 0
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%shamt = shufflevector <4 x i32> %tmp0, <4 x i32> undef, <4 x i32> zeroinitializer
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%shl = shl <4 x i32> %val, %shamt
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store <4 x i32> %shl, <4 x i32>* %dst
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ret void
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}
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define void @shift5d(<4 x i32> %val, <4 x i32>* %dst, i32 %amt) nounwind {
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entry:
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; CHECK: shift5d:
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; CHECK: movd
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; CHECK: psrad
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%tmp0 = insertelement <4 x i32> undef, i32 %amt, i32 0
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%shamt = shufflevector <4 x i32> %tmp0, <4 x i32> undef, <4 x i32> zeroinitializer
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%shr = ashr <4 x i32> %val, %shamt
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store <4 x i32> %shr, <4 x i32>* %dst
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ret void
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}
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