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intrinsics. The second instruction(s) to be handled are the vector versions of count set bits (ctpop). The changes here are to clang so that it generates a target independent vector ctpop when it sees an ARM dependent vector bits set count. The changes in llvm are to match the target independent vector ctpop and in VMCore/AutoUpgrade.cpp to update any existing bc files containing ARM dependent vector pop counts with target-independent ctpops. There are also changes to an existing test case in llvm for ARM vector count instructions and to a test for the bitcode upgrade. <rdar://problem/11892519> There is deliberately no test for the change to clang, as so far as I know, no consensus has been reached regarding how to test neon instructions in clang; q.v. <rdar://problem/8762292> llvm-svn: 160410
22 lines
725 B
LLVM
22 lines
725 B
LLVM
; RUN: llvm-as < %s | llvm-dis | FileCheck %s
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; Tests vclz and vcnt
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define <4 x i16> @vclz16(<4 x i16>* %A) nounwind {
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;CHECK: @vclz16
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%tmp1 = load <4 x i16>* %A
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%tmp2 = call <4 x i16> @llvm.arm.neon.vclz.v4i16(<4 x i16> %tmp1)
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;CHECK: {{call.*@llvm.ctlz.v4i16\(<4 x i16>.*, i1 false}}
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ret <4 x i16> %tmp2
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}
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define <8 x i8> @vcnt8(<8 x i8>* %A) nounwind {
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;CHECK: @vcnt8
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%tmp1 = load <8 x i8>* %A
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%tmp2 = call <8 x i8> @llvm.arm.neon.vcnt.v8i8(<8 x i8> %tmp1)
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;CHECK: call <8 x i8> @llvm.ctpop.v8i8(<8 x i8>
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ret <8 x i8> %tmp2
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}
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declare <4 x i16> @llvm.arm.neon.vclz.v4i16(<4 x i16>) nounwind readnone
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declare <8 x i8> @llvm.arm.neon.vcnt.v8i8(<8 x i8>) nounwind readnone
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