Tim Renouf 524551cd05 [AMDGPU] New buffer intrinsics ... Summary: This commit adds new intrinsics llvm.amdgcn.raw.buffer.load llvm.amdgcn.raw.buffer.load.format llvm.amdgcn.raw.buffer.load.format.d16 llvm.amdgcn.struct.buffer.load llvm.amdgcn.struct.buffer.load.format llvm.amdgcn.struct.buffer.load.format.d16 llvm.amdgcn.raw.buffer.store llvm.amdgcn.raw.buffer.store.format llvm.amdgcn.raw.buffer.store.format.d16 llvm.amdgcn.struct.buffer.store llvm.amdgcn.struct.buffer.store.format llvm.amdgcn.struct.buffer.store.format.d16 llvm.amdgcn.raw.buffer.atomic.* llvm.amdgcn.struct.buffer.atomic.* with the following changes from the llvm.amdgcn.buffer.* intrinsics: * there are separate raw and struct versions: raw does not have an index arg and sets idxen=0 in the instruction, and struct always sets idxen=1 in the instruction even if the index is 0, to allow for the fact that gfx9 does bounds checking differently depending on whether idxen is set; * there is a combined cachepolicy arg (glc+slc) * there are now only two offset args: one for the offset that is included in bounds checking and swizzling, to be split between the instruction's voffset and immoffset fields, and one for the offset that is excluded from bounds checking and swizzling, to go into the instruction's soffset field. The AMDISD::BUFFER_* SD nodes always have an index operand, all three offset operands, combined cachepolicy operand, and an extra idxen operand. The obsolescent llvm.amdgcn.buffer.* intrinsics continue to work. Subscribers: arsenm, kzhuravl, wdng, nhaehnle, yaxunl, dstuttard, t-tye, jfb, llvm-commits Differential Revision: https://reviews.llvm.org/D50306 Change-Id: If897ea7dc34fcbf4d5496e98cc99a934f62fc205 llvm-svn: 340269		2018-08-21 11:07:10 +00:00
..
AMDGPUAsmUtils.cpp	[AMDGPU] Add HW_REG_SH_MEM_BASES symbolic name for s_getreg_b32	2018-01-15 18:49:15 +00:00
AMDGPUAsmUtils.h	[AMDGPU][MC] New syntax for ds_swizzle_b32 offset	2017-05-31 16:26:47 +00:00
AMDGPUBaseInfo.cpp	[AMDGPU] New buffer intrinsics	2018-08-21 11:07:10 +00:00
AMDGPUBaseInfo.h	[AMDGPU] New buffer intrinsics	2018-08-21 11:07:10 +00:00
AMDGPULaneDominator.cpp	AMDGPU: Fix copying i1 value out of loop with non-uniform exit	2018-04-04 10:57:58 +00:00
AMDGPULaneDominator.h	AMDGPU: Fix copying i1 value out of loop with non-uniform exit	2018-04-04 10:57:58 +00:00
AMDKernelCodeTInfo.h	AMDGPU: Remove max_scratch_backing_memory_byte_size from kernel header	2018-04-09 20:47:22 +00:00
AMDKernelCodeTUtils.cpp	[AMDGPU] Fix some Clang-tidy modernize-use-using and Include What You Use warnings; other minor fixes (NFC).	2017-08-10 00:46:15 +00:00
AMDKernelCodeTUtils.h	[AMDGPU] Fix some Clang-tidy modernize-use-using and Include What You Use warnings; other minor fixes (NFC).	2017-08-10 00:46:15 +00:00
CMakeLists.txt	AMDGPU: Fix copying i1 value out of loop with non-uniform exit	2018-04-04 10:57:58 +00:00
LLVMBuild.txt