Akira Hatanaka 3eef445630 [mips] Enhance command line option "-mno-ldc1-sdc1" to expand base+index double ... precision loads and stores as well as reg+imm double precision loads and stores. Previously, expansion of loads and stores was done after register allocation, but now it takes place during legalization. As a result, users will see double precision stores and loads being emitted to spill and restore 64-bit FP registers. llvm-svn: 190235		2013-09-07 00:52:30 +00:00
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AArch64	Inplement aarch64 neon instructions in AdvSIMD(shift). About 24 shift instructions:	2013-09-04 09:28:24 +00:00
ARM	Debug Info Testing: updated to use NULL instead of "i32 0" in a few fields.	2013-09-06 21:03:58 +00:00
CPP
Generic
Hexagon	Debug Info Testing: updated to use NULL instead of "i32 0" in a few fields.	2013-09-06 21:03:58 +00:00
Inputs	Debug Info: add an identifier field to DICompositeType.	2013-08-26 22:39:55 +00:00
Mips	[mips] Enhance command line option "-mno-ldc1-sdc1" to expand base+index double	2013-09-07 00:52:30 +00:00
MSP430
NVPTX	[NVPTX] Re-enable assembly printing support for inline assembly	2013-08-24 01:17:23 +00:00
PowerPC	Debug Info Testing: updated to use NULL instead of "i32 0" in a few fields.	2013-09-06 21:03:58 +00:00
R600	R600: Add support for LDS atomic subtract	2013-09-06 20:17:42 +00:00
SPARC	[Sparc] Correctly handle call to functions with ReturnsTwice attribute.	2013-09-05 05:32:16 +00:00
SystemZ	[SystemZ] Tweak integer comparison code	2013-09-06 11:51:39 +00:00
Thumb	ARM: Use "dmb sy" for barriers on M-class CPUs	2013-08-28 14:39:19 +00:00
Thumb2
X86	Debug Info Testing: updated to use NULL instead of "i32 0" in a few fields.	2013-09-06 21:03:58 +00:00
XCore