Adam Nemet 6d75e0e06f [AVX512] Handle valign masking intrinsic via C++ lowering ... I think that this will scale better in most cases than adding a Pat<> for each mapping from the intrinsic DAG to the intruction (i.e. rri, rrik, rrikz). We can just lower to the SDNode and have the resulting DAG be matches by the DAG patterns. Alternatively (long term), we could keep the Pat<>s but generate them via the new AVX512_masking multiclass. The difficulty is that in order to formulate that we would have to concatenate DAGs. Currently this is only supported if the operators of the input DAGs are identical. llvm-svn: 215473		2014-08-12 21:13:12 +00:00
..
AArch64	[MachineCombiner] Fix for ICE bug 20598	2014-08-12 07:54:12 +00:00
ARM	ARM: try harder to detect non-IT eligible instructions	2014-08-11 20:13:25 +00:00
CPP
Generic
Hexagon	DebugInfo: Assert that any CU for which debug_loc lists are emitted, has at least one range.	2014-08-06 00:21:25 +00:00
Inputs
Mips	Add support for scalarizing cttz_zero_undef	2014-08-10 22:49:54 +00:00
MSP430
NVPTX
PowerPC	Provide an implementation of getNoopForMachoTarget for PPC, otherwise	2014-08-08 19:13:23 +00:00
R600	R600: Use optimized 24bit path in udivrem	2014-08-12 17:31:20 +00:00
SPARC
SystemZ
Thumb	[ARM] In dynamic-no-pic mode, ARM's post-RA pseudo expansion was incorrectly	2014-08-02 05:40:40 +00:00
Thumb2	ARM: do not generate BLX instructions on Cortex-M CPUs.	2014-08-06 11:13:14 +00:00
X86	[AVX512] Handle valign masking intrinsic via C++ lowering	2014-08-12 21:13:12 +00:00
XCore