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3f31269929
This patch adds support for following contiguous load and store instructions: * LD1B, LD1H, LD1W, LD1D, LD1Q * ST1B, ST1H, ST1W, ST1D, ST1Q A new register class and operand is added for the 32-bit vector select register W12-W15. The differences in the following tests which have been re-generated are caused by the introduction of this register class: * llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-inline-asm.ll * llvm/test/CodeGen/AArch64/GlobalISel/regbank-inlineasm.mir * llvm/test/CodeGen/AArch64/stp-opt-with-renaming-reserved-regs.mir * llvm/test/CodeGen/AArch64/stp-opt-with-renaming.mir D88663 attempts to resolve the issue with the store pair test differences in the AArch64 load/store optimizer. The GlobalISel differences are caused by changes in the enum values of register classes, tests have been updated with the new values. The reference can be found here: https://developer.arm.com/documentation/ddi0602/2021-06 Reviewed By: CarolineConcatto Differential Revision: https://reviews.llvm.org/D105572 |
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| Analysis | ||
| Assembler | ||
| Bindings | ||
| Bitcode | ||
| BugPoint | ||
| CodeGen | ||
| DebugInfo | ||
| Demangle | ||
| Examples | ||
| ExecutionEngine | ||
| Feature | ||
| FileCheck | ||
| Instrumentation | ||
| Integer | ||
| JitListener | ||
| Linker | ||
| LTO | ||
| MachineVerifier | ||
| MC | ||
| Object | ||
| ObjectYAML | ||
| Other | ||
| SafepointIRVerifier | ||
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| SymbolRewriter | ||
| TableGen | ||
| ThinLTO/X86 | ||
| tools | ||
| Transforms | ||
| Unit | ||
| Verifier | ||
| YAMLParser | ||
| .clang-format | ||
| CMakeLists.txt | ||
| lit.cfg.py | ||
| lit.site.cfg.py.in | ||
| TestRunner.sh | ||