mirror of
https://github.com/RPCS3/llvm-mirror.git
synced 2024-11-24 11:42:57 +01:00
3f9ad6b478
This re-commits everything that was pulled in r314244. The transformation is off by default (patch to enable it to follow). The code is refactored to have a single entry-point and provide fine-grained control over patterns that it selects. This patch also fixes the bugs in the original code. Everything that failed with the original patch has been re-tested with this patch (with the transformation turned on). So the patch to turn this on is soon to follow. Differential Revision: https://reviews.llvm.org/D38575 llvm-svn: 319434
69 lines
2.2 KiB
LLVM
69 lines
2.2 KiB
LLVM
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
|
|
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
|
|
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
|
|
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
|
|
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
|
|
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
|
|
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
|
|
@glob = common local_unnamed_addr global i8 0, align 1
|
|
|
|
define signext i32 @test_ilesc(i8 signext %a, i8 signext %b) {
|
|
; CHECK-LABEL: test_ilesc:
|
|
; CHECK: # BB#0: # %entry
|
|
; CHECK-NEXT: sub r3, r4, r3
|
|
; CHECK-NEXT: rldicl r3, r3, 1, 63
|
|
; CHECK-NEXT: xori r3, r3, 1
|
|
; CHECK-NEXT: blr
|
|
entry:
|
|
%cmp = icmp sle i8 %a, %b
|
|
%conv2 = zext i1 %cmp to i32
|
|
ret i32 %conv2
|
|
}
|
|
|
|
define signext i32 @test_ilesc_sext(i8 signext %a, i8 signext %b) {
|
|
; CHECK-LABEL: test_ilesc_sext:
|
|
; CHECK: # BB#0: # %entry
|
|
; CHECK-NEXT: sub r3, r4, r3
|
|
; CHECK-NEXT: rldicl r3, r3, 1, 63
|
|
; CHECK-NEXT: addi r3, r3, -1
|
|
; CHECK-NEXT: blr
|
|
entry:
|
|
%cmp = icmp sle i8 %a, %b
|
|
%sub = sext i1 %cmp to i32
|
|
ret i32 %sub
|
|
}
|
|
|
|
define void @test_ilesc_store(i8 signext %a, i8 signext %b) {
|
|
; CHECK-LABEL: test_ilesc_store:
|
|
; CHECK: # BB#0: # %entry
|
|
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
|
|
; CHECK-NEXT: sub r3, r4, r3
|
|
; CHECK-NEXT: ld r12, .LC0@toc@l(r5)
|
|
; CHECK-NEXT: rldicl r3, r3, 1, 63
|
|
; CHECK-NEXT: xori r3, r3, 1
|
|
; CHECK-NEXT: stb r3, 0(r12)
|
|
; CHECK-NEXT: blr
|
|
entry:
|
|
%cmp = icmp sle i8 %a, %b
|
|
%conv3 = zext i1 %cmp to i8
|
|
store i8 %conv3, i8* @glob, align 1
|
|
ret void
|
|
}
|
|
|
|
define void @test_ilesc_sext_store(i8 signext %a, i8 signext %b) {
|
|
; CHECK-LABEL: test_ilesc_sext_store:
|
|
; CHECK: # BB#0: # %entry
|
|
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
|
|
; CHECK-NEXT: sub r3, r4, r3
|
|
; CHECK-NEXT: ld r12, .LC0@toc@l(r5)
|
|
; CHECK-NEXT: rldicl r3, r3, 1, 63
|
|
; CHECK-NEXT: addi r3, r3, -1
|
|
; CHECK-NEXT: stb r3, 0(r12)
|
|
; CHECK-NEXT: blr
|
|
entry:
|
|
%cmp = icmp sle i8 %a, %b
|
|
%conv3 = sext i1 %cmp to i8
|
|
store i8 %conv3, i8* @glob, align 1
|
|
ret void
|
|
}
|