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437c838680
The missed load folding noticed in D55898 is visible independent of that change either with an adjusted IR pattern to start or with AVX2/AVX512 (where the build vector becomes a broadcast first; movddup is not produced until we get into isel via tablegen patterns). Differential Revision: https://reviews.llvm.org/D55936 llvm-svn: 350005
25 lines
1.0 KiB
LLVM
25 lines
1.0 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=i686-- -mattr=+sse4.1 | FileCheck %s --check-prefixes=SSE,SSE41
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; RUN: llc < %s -mtriple=i686-- -mattr=+avx | FileCheck %s --check-prefixes=AVX,AVX1
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; RUN: llc < %s -mtriple=i686-- -mattr=+avx2 | FileCheck %s --check-prefixes=AVX,AVX2
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; RUN: llc < %s -mtriple=i686-- -mattr=+avx512vl | FileCheck %s --check-prefixes=AVX,AVX512VL
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; Test an isel pattern for a splatted VZLOAD.
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define <4 x float> @movddup_load_fold(float %x, float %y) {
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; SSE-LABEL: movddup_load_fold:
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; SSE: # %bb.0:
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; SSE-NEXT: movddup {{.*#+}} xmm0 = mem[0,0]
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; SSE-NEXT: retl
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;
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; AVX-LABEL: movddup_load_fold:
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; AVX: # %bb.0:
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; AVX-NEXT: vmovddup {{.*#+}} xmm0 = mem[0,0]
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; AVX-NEXT: retl
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%i0 = insertelement <4 x float> zeroinitializer, float %x, i32 0
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%i1 = insertelement <4 x float> %i0, float %y, i32 1
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%dup = shufflevector <4 x float> %i1, <4 x float> undef, <4 x i32> <i32 0, i32 1, i32 0, i32 1>
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ret <4 x float> %dup
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}
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