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556791680d
Summary: The bugs were: * append, prepend, and balign were not tested * balign takes a uimm2 not a uimm5. * drotr32 was correctly implemented with a uimm5 but the tests expected '52' to be valid. * li/la were implemented with a uimm5 instead of simm32. simm32 isn't completely correct either but I'll fix that when I get to simm32. A notable omission are some of the shift instructions. Several of these have been implemented using a single uimm6 instruction (rather than two uimm5 instructions and a CodeGen-only uimm6 pseudo). These will be updated in the uimm6 patch. Reviewers: vkalintiris Subscribers: llvm-commits, dsanders Differential Revision: http://reviews.llvm.org/D14712 llvm-svn: 254164
16 lines
885 B
ArmAsm
16 lines
885 B
ArmAsm
# Instructions that are invalid
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#
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# RUN: not llvm-mc %s -triple=mips64-unknown-linux -show-encoding -mcpu=octeon 2>%t1
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# RUN: FileCheck %s < %t1
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.set noat
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foo:
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bbit0 $19, -1, foo # CHECK: :[[@LINE]]:16: error: expected 6-bit unsigned immediate
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bbit0 $19, 64, foo # CHECK: :[[@LINE]]:16: error: expected 6-bit unsigned immediate
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bbit032 $19, -1, foo # CHECK: :[[@LINE]]:18: error: expected 5-bit unsigned immediate
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bbit032 $19, 32, foo # CHECK: :[[@LINE]]:18: error: expected 5-bit unsigned immediate
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bbit1 $19, -1, foo # CHECK: :[[@LINE]]:16: error: expected 6-bit unsigned immediate
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bbit1 $19, 64, foo # CHECK: :[[@LINE]]:16: error: expected 6-bit unsigned immediate
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bbit132 $19, -1, foo # CHECK: :[[@LINE]]:18: error: expected 5-bit unsigned immediate
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bbit132 $19, 32, foo # CHECK: :[[@LINE]]:18: error: expected 5-bit unsigned immediate
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