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llvm-mirror/lib/CodeGen/SelectionDAG
Adam Nemet 3fe531df7b [ISel] Keep matching state consistent when folding during X86 address match
In the X86 backend, matching an address is initiated by the 'addr' complex
pattern and its friends.  During this process we may reassociate and-of-shift
into shift-of-and (FoldMaskedShiftToScaledMask) to allow folding of the
shift into the scale of the address.

However as demonstrated by the testcase, this can trigger CSE of not only the
shift and the AND which the code is prepared for but also the underlying load
node.  In the testcase this node is sitting in the RecordedNode and MatchScope
data structures of the matcher and becomes a deleted node upon CSE.  Returning
from the complex pattern function, we try to access it again hitting an assert
because the node is no longer a load even though this was checked before.

Now obviously changing the DAG this late is bending the rules but I think it
makes sense somewhat.  Outside of addresses we prefer and-of-shift because it
may lead to smaller immediates (FoldMaskAndShiftToScale is an even better
example because it create a non-canonical node).  We currently don't recognize
addresses during DAGCombiner where arguably this canonicalization should be
performed.  On the other hand, having this in the matcher allows us to cover
all the cases where an address can be used in an instruction.

I've also talked a little bit to Dan Gohman on llvm-dev who added the RAUW for
the new shift node in FoldMaskedShiftToScaledMask.  This RAUW is responsible
for initiating the recursive CSE on users
(http://lists.cs.uiuc.edu/pipermail/llvmdev/2014-September/076903.html) but it
is not strictly necessary since the shift is hooked into the visited user.  Of
course it's safer to keep the DAG consistent at all times (e.g. for accurate
number of uses, etc.).

So rather than changing the fundamentals, I've decided to continue along the
previous patches and detect the CSE.  This patch installs a very targeted
DAGUpdateListener for the duration of a complex-pattern match and updates the
matching state accordingly.  (Previous patches used HandleSDNode to detect the
CSE but that's not practical here).  The listener is only installed on X86.

I tested that there is no measurable overhead due to this while running
through the spec2k BC files with llc.  The only thing we pay for is the
creation of the listener.  The callback never ever triggers in spec2k since
this is a corner case.

Fixes rdar://problem/18206171

llvm-svn: 219009
2014-10-03 20:00:34 +00:00
..
CMakeLists.txt llvm/lib: [CMake] Add explicit dependency to intrinsics_gen. 2012-06-24 13:32:01 +00:00
DAGCombiner.cpp Use the target-specified iteration count to opt out of any further refinement of an estimate. NFC. 2014-09-30 20:44:23 +00:00
FastISel.cpp Move the complex address expression out of DIVariable and into an extra 2014-10-01 18:55:02 +00:00
FunctionLoweringInfo.cpp Move the complex address expression out of DIVariable and into an extra 2014-10-01 18:55:02 +00:00
InstrEmitter.cpp Move the complex address expression out of DIVariable and into an extra 2014-10-01 18:55:02 +00:00
InstrEmitter.h Canonicalize header guards into a common format. 2014-08-13 16:26:38 +00:00
LegalizeDAG.cpp Replace dead links to "Hacker's Delight" with general references. NFC. 2014-09-15 19:47:44 +00:00
LegalizeFloatTypes.cpp ARM: fix @llvm.convert.from.fp16 on softfloat targets. 2014-07-29 09:56:38 +00:00
LegalizeIntegerTypes.cpp Optimize sext/zext insertion algorithm in back-end. 2014-09-19 05:30:35 +00:00
LegalizeTypes.cpp Make it possible for ints/floats to return different values from getBooleanContents() 2014-07-10 10:18:12 +00:00
LegalizeTypes.h Canonicalize header guards into a common format. 2014-08-13 16:26:38 +00:00
LegalizeTypesGeneric.cpp AA metadata refactoring (introduce AAMDNodes) 2014-07-24 12:16:19 +00:00
LegalizeVectorOps.cpp Teach the AArch64 backend about v4f16 and v8f16 2014-08-27 16:16:04 +00:00
LegalizeVectorTypes.cpp Allow targets to custom legalize vector insertion and extraction. 2014-09-12 22:16:11 +00:00
LLVMBuild.txt
Makefile
ResourcePriorityQueue.cpp Change MCSchedModel to be a struct of statically initialized data. 2014-09-02 17:43:54 +00:00
ScheduleDAGFast.cpp [Modules] Remove potential ODR violations by sinking the DEBUG_TYPE 2014-04-22 02:02:50 +00:00
ScheduleDAGRRList.cpp Remove the TargetMachine forwards for TargetSubtargetInfo based 2014-08-04 21:25:23 +00:00
ScheduleDAGSDNodes.cpp Make this SmallVector size a power of two as suggested by Chandler 2014-08-11 13:47:57 +00:00
ScheduleDAGSDNodes.h Canonicalize header guards into a common format. 2014-08-13 16:26:38 +00:00
ScheduleDAGVLIW.cpp Remove the TargetMachine forwards for TargetSubtargetInfo based 2014-08-04 21:25:23 +00:00
SDNodeDbgValue.h Move the complex address expression out of DIVariable and into an extra 2014-10-01 18:55:02 +00:00
SelectionDAG.cpp Move the complex address expression out of DIVariable and into an extra 2014-10-01 18:55:02 +00:00
SelectionDAGBuilder.cpp Move the complex address expression out of DIVariable and into an extra 2014-10-01 18:55:02 +00:00
SelectionDAGBuilder.h Move the complex address expression out of DIVariable and into an extra 2014-10-01 18:55:02 +00:00
SelectionDAGDumper.cpp Have MachineFunction cache a pointer to the subtarget to make lookups 2014-08-05 02:39:49 +00:00
SelectionDAGISel.cpp [ISel] Keep matching state consistent when folding during X86 address match 2014-10-03 20:00:34 +00:00
SelectionDAGPrinter.cpp Revert "Introduce a string_ostream string builder facilty" 2014-06-26 22:52:05 +00:00
TargetLowering.cpp Eliminate some deep std::vector copies. NFC. 2014-10-03 18:33:16 +00:00
TargetSelectionDAGInfo.cpp Have TargetSelectionDAGInfo take a DataLayout initializer rather than 2014-06-06 19:04:48 +00:00