Tom Stellard 40599ea21b AMDGPU/SI: Handle hazard with sgpr lane selects for v_{read,write}lane ... Reviewers: arsenm Subscribers: kzhuravl, wdng, nhaehnle, yaxunl, tony-tye, llvm-commits Differential Revision: https://reviews.llvm.org/D25637 llvm-svn: 285367		2016-10-27 23:42:29 +00:00
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AArch64	Add AArch64 unit tests	2016-10-12 09:00:44 +00:00
AMDGPU	AMDGPU/SI: Handle hazard with sgpr lane selects for v_{read,write}lane	2016-10-27 23:42:29 +00:00
ARM	MachineFunctionProperties/MIRParser: Rename AllVRegsAllocated->NoVRegs, compute it	2016-08-25 01:27:13 +00:00
Generic	MIRParser/MIRPrinter: Compute HasInlineAsm instead of printing/parsing it	2016-08-24 22:34:06 +00:00
Hexagon	[MIRParser] Parse lane masks for register live-ins	2016-10-12 21:06:45 +00:00
Lanai	MachineFunctionProperties/MIRParser: Rename AllVRegsAllocated->NoVRegs, compute it	2016-08-25 01:27:13 +00:00
Mips	MIRParser: Use shorter cfi identifiers	2016-07-26 18:20:00 +00:00
NVPTX	llc: Add support for -run-pass none	2016-07-16 02:24:59 +00:00
PowerPC	MIRParser/MIRPrinter: Compute isSSA instead of printing/parsing it.	2016-08-24 01:32:41 +00:00
X86	MIRParser: Rewrite register info initialization; mostly NFC	2016-10-11 03:13:01 +00:00