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https://github.com/RPCS3/llvm-mirror.git
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807d004452
IR add/sub operations with one or both operands sign- or zero-extended. Auto-upgrade the old intrinsics. llvm-svn: 112416
280 lines
7.6 KiB
LLVM
280 lines
7.6 KiB
LLVM
; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
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define <8 x i8> @vsubi8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
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;CHECK: vsubi8:
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;CHECK: vsub.i8
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%tmp1 = load <8 x i8>* %A
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%tmp2 = load <8 x i8>* %B
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%tmp3 = sub <8 x i8> %tmp1, %tmp2
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ret <8 x i8> %tmp3
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}
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define <4 x i16> @vsubi16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
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;CHECK: vsubi16:
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;CHECK: vsub.i16
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%tmp1 = load <4 x i16>* %A
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%tmp2 = load <4 x i16>* %B
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%tmp3 = sub <4 x i16> %tmp1, %tmp2
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ret <4 x i16> %tmp3
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}
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define <2 x i32> @vsubi32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
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;CHECK: vsubi32:
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;CHECK: vsub.i32
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%tmp1 = load <2 x i32>* %A
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%tmp2 = load <2 x i32>* %B
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%tmp3 = sub <2 x i32> %tmp1, %tmp2
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ret <2 x i32> %tmp3
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}
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define <1 x i64> @vsubi64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
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;CHECK: vsubi64:
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;CHECK: vsub.i64
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%tmp1 = load <1 x i64>* %A
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%tmp2 = load <1 x i64>* %B
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%tmp3 = sub <1 x i64> %tmp1, %tmp2
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ret <1 x i64> %tmp3
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}
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define <2 x float> @vsubf32(<2 x float>* %A, <2 x float>* %B) nounwind {
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;CHECK: vsubf32:
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;CHECK: vsub.f32
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%tmp1 = load <2 x float>* %A
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%tmp2 = load <2 x float>* %B
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%tmp3 = fsub <2 x float> %tmp1, %tmp2
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ret <2 x float> %tmp3
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}
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define <16 x i8> @vsubQi8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
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;CHECK: vsubQi8:
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;CHECK: vsub.i8
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%tmp1 = load <16 x i8>* %A
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%tmp2 = load <16 x i8>* %B
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%tmp3 = sub <16 x i8> %tmp1, %tmp2
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ret <16 x i8> %tmp3
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}
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define <8 x i16> @vsubQi16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
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;CHECK: vsubQi16:
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;CHECK: vsub.i16
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%tmp1 = load <8 x i16>* %A
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%tmp2 = load <8 x i16>* %B
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%tmp3 = sub <8 x i16> %tmp1, %tmp2
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ret <8 x i16> %tmp3
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}
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define <4 x i32> @vsubQi32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
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;CHECK: vsubQi32:
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;CHECK: vsub.i32
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%tmp1 = load <4 x i32>* %A
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%tmp2 = load <4 x i32>* %B
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%tmp3 = sub <4 x i32> %tmp1, %tmp2
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ret <4 x i32> %tmp3
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}
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define <2 x i64> @vsubQi64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
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;CHECK: vsubQi64:
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;CHECK: vsub.i64
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%tmp1 = load <2 x i64>* %A
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%tmp2 = load <2 x i64>* %B
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%tmp3 = sub <2 x i64> %tmp1, %tmp2
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ret <2 x i64> %tmp3
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}
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define <4 x float> @vsubQf32(<4 x float>* %A, <4 x float>* %B) nounwind {
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;CHECK: vsubQf32:
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;CHECK: vsub.f32
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%tmp1 = load <4 x float>* %A
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%tmp2 = load <4 x float>* %B
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%tmp3 = fsub <4 x float> %tmp1, %tmp2
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ret <4 x float> %tmp3
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}
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define <8 x i8> @vsubhni16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
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;CHECK: vsubhni16:
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;CHECK: vsubhn.i16
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%tmp1 = load <8 x i16>* %A
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%tmp2 = load <8 x i16>* %B
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%tmp3 = call <8 x i8> @llvm.arm.neon.vsubhn.v8i8(<8 x i16> %tmp1, <8 x i16> %tmp2)
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ret <8 x i8> %tmp3
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}
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define <4 x i16> @vsubhni32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
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;CHECK: vsubhni32:
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;CHECK: vsubhn.i32
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%tmp1 = load <4 x i32>* %A
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%tmp2 = load <4 x i32>* %B
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%tmp3 = call <4 x i16> @llvm.arm.neon.vsubhn.v4i16(<4 x i32> %tmp1, <4 x i32> %tmp2)
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ret <4 x i16> %tmp3
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}
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define <2 x i32> @vsubhni64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
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;CHECK: vsubhni64:
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;CHECK: vsubhn.i64
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%tmp1 = load <2 x i64>* %A
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%tmp2 = load <2 x i64>* %B
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%tmp3 = call <2 x i32> @llvm.arm.neon.vsubhn.v2i32(<2 x i64> %tmp1, <2 x i64> %tmp2)
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ret <2 x i32> %tmp3
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}
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declare <8 x i8> @llvm.arm.neon.vsubhn.v8i8(<8 x i16>, <8 x i16>) nounwind readnone
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declare <4 x i16> @llvm.arm.neon.vsubhn.v4i16(<4 x i32>, <4 x i32>) nounwind readnone
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declare <2 x i32> @llvm.arm.neon.vsubhn.v2i32(<2 x i64>, <2 x i64>) nounwind readnone
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define <8 x i8> @vrsubhni16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
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;CHECK: vrsubhni16:
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;CHECK: vrsubhn.i16
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%tmp1 = load <8 x i16>* %A
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%tmp2 = load <8 x i16>* %B
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%tmp3 = call <8 x i8> @llvm.arm.neon.vrsubhn.v8i8(<8 x i16> %tmp1, <8 x i16> %tmp2)
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ret <8 x i8> %tmp3
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}
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define <4 x i16> @vrsubhni32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
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;CHECK: vrsubhni32:
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;CHECK: vrsubhn.i32
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%tmp1 = load <4 x i32>* %A
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%tmp2 = load <4 x i32>* %B
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%tmp3 = call <4 x i16> @llvm.arm.neon.vrsubhn.v4i16(<4 x i32> %tmp1, <4 x i32> %tmp2)
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ret <4 x i16> %tmp3
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}
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define <2 x i32> @vrsubhni64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
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;CHECK: vrsubhni64:
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;CHECK: vrsubhn.i64
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%tmp1 = load <2 x i64>* %A
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%tmp2 = load <2 x i64>* %B
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%tmp3 = call <2 x i32> @llvm.arm.neon.vrsubhn.v2i32(<2 x i64> %tmp1, <2 x i64> %tmp2)
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ret <2 x i32> %tmp3
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}
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declare <8 x i8> @llvm.arm.neon.vrsubhn.v8i8(<8 x i16>, <8 x i16>) nounwind readnone
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declare <4 x i16> @llvm.arm.neon.vrsubhn.v4i16(<4 x i32>, <4 x i32>) nounwind readnone
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declare <2 x i32> @llvm.arm.neon.vrsubhn.v2i32(<2 x i64>, <2 x i64>) nounwind readnone
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define <8 x i16> @vsubls8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
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;CHECK: vsubls8:
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;CHECK: vsubl.s8
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%tmp1 = load <8 x i8>* %A
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%tmp2 = load <8 x i8>* %B
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%tmp3 = sext <8 x i8> %tmp1 to <8 x i16>
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%tmp4 = sext <8 x i8> %tmp2 to <8 x i16>
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%tmp5 = sub <8 x i16> %tmp3, %tmp4
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ret <8 x i16> %tmp5
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}
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define <4 x i32> @vsubls16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
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;CHECK: vsubls16:
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;CHECK: vsubl.s16
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%tmp1 = load <4 x i16>* %A
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%tmp2 = load <4 x i16>* %B
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%tmp3 = sext <4 x i16> %tmp1 to <4 x i32>
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%tmp4 = sext <4 x i16> %tmp2 to <4 x i32>
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%tmp5 = sub <4 x i32> %tmp3, %tmp4
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ret <4 x i32> %tmp5
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}
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define <2 x i64> @vsubls32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
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;CHECK: vsubls32:
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;CHECK: vsubl.s32
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%tmp1 = load <2 x i32>* %A
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%tmp2 = load <2 x i32>* %B
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%tmp3 = sext <2 x i32> %tmp1 to <2 x i64>
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%tmp4 = sext <2 x i32> %tmp2 to <2 x i64>
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%tmp5 = sub <2 x i64> %tmp3, %tmp4
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ret <2 x i64> %tmp5
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}
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define <8 x i16> @vsublu8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
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;CHECK: vsublu8:
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;CHECK: vsubl.u8
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%tmp1 = load <8 x i8>* %A
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%tmp2 = load <8 x i8>* %B
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%tmp3 = zext <8 x i8> %tmp1 to <8 x i16>
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%tmp4 = zext <8 x i8> %tmp2 to <8 x i16>
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%tmp5 = sub <8 x i16> %tmp3, %tmp4
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ret <8 x i16> %tmp5
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}
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define <4 x i32> @vsublu16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
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;CHECK: vsublu16:
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;CHECK: vsubl.u16
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%tmp1 = load <4 x i16>* %A
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%tmp2 = load <4 x i16>* %B
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%tmp3 = zext <4 x i16> %tmp1 to <4 x i32>
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%tmp4 = zext <4 x i16> %tmp2 to <4 x i32>
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%tmp5 = sub <4 x i32> %tmp3, %tmp4
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ret <4 x i32> %tmp5
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}
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define <2 x i64> @vsublu32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
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;CHECK: vsublu32:
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;CHECK: vsubl.u32
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%tmp1 = load <2 x i32>* %A
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%tmp2 = load <2 x i32>* %B
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%tmp3 = zext <2 x i32> %tmp1 to <2 x i64>
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%tmp4 = zext <2 x i32> %tmp2 to <2 x i64>
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%tmp5 = sub <2 x i64> %tmp3, %tmp4
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ret <2 x i64> %tmp5
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}
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define <8 x i16> @vsubws8(<8 x i16>* %A, <8 x i8>* %B) nounwind {
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;CHECK: vsubws8:
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;CHECK: vsubw.s8
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%tmp1 = load <8 x i16>* %A
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%tmp2 = load <8 x i8>* %B
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%tmp3 = sext <8 x i8> %tmp2 to <8 x i16>
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%tmp4 = sub <8 x i16> %tmp1, %tmp3
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ret <8 x i16> %tmp4
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}
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define <4 x i32> @vsubws16(<4 x i32>* %A, <4 x i16>* %B) nounwind {
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;CHECK: vsubws16:
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;CHECK: vsubw.s16
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%tmp1 = load <4 x i32>* %A
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%tmp2 = load <4 x i16>* %B
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%tmp3 = sext <4 x i16> %tmp2 to <4 x i32>
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%tmp4 = sub <4 x i32> %tmp1, %tmp3
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ret <4 x i32> %tmp4
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}
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define <2 x i64> @vsubws32(<2 x i64>* %A, <2 x i32>* %B) nounwind {
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;CHECK: vsubws32:
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;CHECK: vsubw.s32
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%tmp1 = load <2 x i64>* %A
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%tmp2 = load <2 x i32>* %B
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%tmp3 = sext <2 x i32> %tmp2 to <2 x i64>
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%tmp4 = sub <2 x i64> %tmp1, %tmp3
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ret <2 x i64> %tmp4
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}
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define <8 x i16> @vsubwu8(<8 x i16>* %A, <8 x i8>* %B) nounwind {
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;CHECK: vsubwu8:
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;CHECK: vsubw.u8
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%tmp1 = load <8 x i16>* %A
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%tmp2 = load <8 x i8>* %B
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%tmp3 = zext <8 x i8> %tmp2 to <8 x i16>
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%tmp4 = sub <8 x i16> %tmp1, %tmp3
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ret <8 x i16> %tmp4
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}
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define <4 x i32> @vsubwu16(<4 x i32>* %A, <4 x i16>* %B) nounwind {
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;CHECK: vsubwu16:
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;CHECK: vsubw.u16
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%tmp1 = load <4 x i32>* %A
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%tmp2 = load <4 x i16>* %B
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%tmp3 = zext <4 x i16> %tmp2 to <4 x i32>
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%tmp4 = sub <4 x i32> %tmp1, %tmp3
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ret <4 x i32> %tmp4
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}
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define <2 x i64> @vsubwu32(<2 x i64>* %A, <2 x i32>* %B) nounwind {
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;CHECK: vsubwu32:
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;CHECK: vsubw.u32
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%tmp1 = load <2 x i64>* %A
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%tmp2 = load <2 x i32>* %B
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%tmp3 = zext <2 x i32> %tmp2 to <2 x i64>
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%tmp4 = sub <2 x i64> %tmp1, %tmp3
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ret <2 x i64> %tmp4
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}
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