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40fc5609c6
This adds the IIC_ prefix to the instruction itinerary class names, giving the PPC backend a naming convention for itinerary classes that is more consistent with that used by the X86 and ARM backends. Instruction scheduling in the PPC backend needs a bunch of cleanup and improvement (especially for the ooo cores). This is just a preliminary step. No functionality change intended. llvm-svn: 195890
72 lines
3.7 KiB
TableGen
72 lines
3.7 KiB
TableGen
//===-- PPCScheduleG3.td - PPC G3 Scheduling Definitions ---*- tablegen -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines the itinerary class data for the G3 (750) processor.
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//
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//===----------------------------------------------------------------------===//
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def G3Itineraries : ProcessorItineraries<
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[IU1, IU2, FPU1, BPU, SRU, SLU], [], [
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InstrItinData<IIC_IntSimple , [InstrStage<1, [IU1, IU2]>]>,
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InstrItinData<IIC_IntGeneral , [InstrStage<1, [IU1, IU2]>]>,
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InstrItinData<IIC_IntCompare , [InstrStage<1, [IU1, IU2]>]>,
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InstrItinData<IIC_IntDivW , [InstrStage<19, [IU1]>]>,
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InstrItinData<IIC_IntMFFS , [InstrStage<1, [FPU1]>]>,
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InstrItinData<IIC_IntMTFSB0 , [InstrStage<3, [FPU1]>]>,
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InstrItinData<IIC_IntMulHW , [InstrStage<5, [IU1]>]>,
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InstrItinData<IIC_IntMulHWU , [InstrStage<6, [IU1]>]>,
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InstrItinData<IIC_IntMulLI , [InstrStage<3, [IU1]>]>,
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InstrItinData<IIC_IntRotate , [InstrStage<1, [IU1, IU2]>]>,
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InstrItinData<IIC_IntShift , [InstrStage<1, [IU1, IU2]>]>,
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InstrItinData<IIC_IntTrapW , [InstrStage<2, [IU1, IU2]>]>,
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InstrItinData<IIC_BrB , [InstrStage<1, [BPU]>]>,
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InstrItinData<IIC_BrCR , [InstrStage<1, [SRU]>]>,
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InstrItinData<IIC_BrMCR , [InstrStage<1, [SRU]>]>,
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InstrItinData<IIC_BrMCRX , [InstrStage<1, [SRU]>]>,
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InstrItinData<IIC_LdStDCBA , [InstrStage<2, [SLU]>]>,
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InstrItinData<IIC_LdStDCBF , [InstrStage<3, [SLU]>]>,
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InstrItinData<IIC_LdStDCBI , [InstrStage<3, [SLU]>]>,
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InstrItinData<IIC_LdStLoad , [InstrStage<2, [SLU]>]>,
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InstrItinData<IIC_LdStLoadUpd , [InstrStage<2, [SLU]>]>,
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InstrItinData<IIC_LdStStore , [InstrStage<2, [SLU]>]>,
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InstrItinData<IIC_LdStStoreUpd, [InstrStage<2, [SLU]>]>,
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InstrItinData<IIC_LdStICBI , [InstrStage<3, [SLU]>]>,
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InstrItinData<IIC_LdStSTFD , [InstrStage<2, [SLU]>]>,
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InstrItinData<IIC_LdStSTFDU , [InstrStage<2, [SLU]>]>,
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InstrItinData<IIC_LdStLFD , [InstrStage<2, [SLU]>]>,
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InstrItinData<IIC_LdStLFDU , [InstrStage<2, [SLU]>]>,
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InstrItinData<IIC_LdStLHA , [InstrStage<2, [SLU]>]>,
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InstrItinData<IIC_LdStLHAU , [InstrStage<2, [SLU]>]>,
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InstrItinData<IIC_LdStLMW , [InstrStage<34, [SLU]>]>,
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InstrItinData<IIC_LdStLWARX , [InstrStage<3, [SLU]>]>,
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InstrItinData<IIC_LdStSTWCX , [InstrStage<8, [SLU]>]>,
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InstrItinData<IIC_LdStSync , [InstrStage<3, [SLU]>]>,
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InstrItinData<IIC_SprISYNC , [InstrStage<2, [SRU]>]>,
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InstrItinData<IIC_SprMFSR , [InstrStage<3, [SRU]>]>,
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InstrItinData<IIC_SprMTMSR , [InstrStage<1, [SRU]>]>,
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InstrItinData<IIC_SprMTSR , [InstrStage<2, [SRU]>]>,
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InstrItinData<IIC_SprTLBSYNC , [InstrStage<3, [SRU]>]>,
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InstrItinData<IIC_SprMFCR , [InstrStage<1, [SRU]>]>,
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InstrItinData<IIC_SprMFMSR , [InstrStage<1, [SRU]>]>,
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InstrItinData<IIC_SprMFSPR , [InstrStage<3, [SRU]>]>,
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InstrItinData<IIC_SprMFTB , [InstrStage<3, [SRU]>]>,
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InstrItinData<IIC_SprMTSPR , [InstrStage<2, [SRU]>]>,
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InstrItinData<IIC_SprMTSRIN , [InstrStage<2, [SRU]>]>,
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InstrItinData<IIC_SprRFI , [InstrStage<2, [SRU]>]>,
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InstrItinData<IIC_SprSC , [InstrStage<2, [SRU]>]>,
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InstrItinData<IIC_FPGeneral , [InstrStage<1, [FPU1]>]>,
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InstrItinData<IIC_FPAddSub , [InstrStage<1, [FPU1]>]>,
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InstrItinData<IIC_FPCompare , [InstrStage<1, [FPU1]>]>,
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InstrItinData<IIC_FPDivD , [InstrStage<31, [FPU1]>]>,
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InstrItinData<IIC_FPDivS , [InstrStage<17, [FPU1]>]>,
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InstrItinData<IIC_FPFused , [InstrStage<2, [FPU1]>]>,
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InstrItinData<IIC_FPRes , [InstrStage<10, [FPU1]>]>
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]>;
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