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40fc5609c6
This adds the IIC_ prefix to the instruction itinerary class names, giving the PPC backend a naming convention for itinerary classes that is more consistent with that used by the X86 and ARM backends. Instruction scheduling in the PPC backend needs a bunch of cleanup and improvement (especially for the ooo cores). This is just a preliminary step. No functionality change intended. llvm-svn: 195890
89 lines
4.9 KiB
TableGen
89 lines
4.9 KiB
TableGen
//===-- PPCScheduleG4Plus.td - PPC G4+ Scheduling Defs. ----*- tablegen -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines the itinerary class data for the G4+ (7450) processor.
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//
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//===----------------------------------------------------------------------===//
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def IU3 : FuncUnit; // integer unit 3 (7450 simple)
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def IU4 : FuncUnit; // integer unit 4 (7450 simple)
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def G4PlusItineraries : ProcessorItineraries<
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[IU1, IU2, IU3, IU4, BPU, SLU, FPU1, VFPU, VIU1, VIU2, VPU], [], [
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InstrItinData<IIC_IntSimple , [InstrStage<1, [IU1, IU2, IU3, IU4]>]>,
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InstrItinData<IIC_IntGeneral , [InstrStage<1, [IU1, IU2, IU3, IU4]>]>,
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InstrItinData<IIC_IntCompare , [InstrStage<1, [IU1, IU2, IU3, IU4]>]>,
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InstrItinData<IIC_IntDivW , [InstrStage<23, [IU2]>]>,
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InstrItinData<IIC_IntMFFS , [InstrStage<5, [FPU1]>]>,
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InstrItinData<IIC_IntMFVSCR , [InstrStage<2, [VFPU]>]>,
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InstrItinData<IIC_IntMTFSB0 , [InstrStage<5, [FPU1]>]>,
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InstrItinData<IIC_IntMulHW , [InstrStage<4, [IU2]>]>,
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InstrItinData<IIC_IntMulHWU , [InstrStage<4, [IU2]>]>,
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InstrItinData<IIC_IntMulLI , [InstrStage<3, [IU2]>]>,
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InstrItinData<IIC_IntRotate , [InstrStage<1, [IU1, IU2, IU3, IU4]>]>,
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InstrItinData<IIC_IntShift , [InstrStage<2, [IU1, IU2, IU3, IU4]>]>,
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InstrItinData<IIC_IntTrapW , [InstrStage<2, [IU1, IU2, IU3, IU4]>]>,
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InstrItinData<IIC_BrB , [InstrStage<1, [BPU]>]>,
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InstrItinData<IIC_BrCR , [InstrStage<2, [IU2]>]>,
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InstrItinData<IIC_BrMCR , [InstrStage<2, [IU2]>]>,
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InstrItinData<IIC_BrMCRX , [InstrStage<2, [IU2]>]>,
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InstrItinData<IIC_LdStDCBF , [InstrStage<3, [SLU]>]>,
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InstrItinData<IIC_LdStDCBI , [InstrStage<3, [SLU]>]>,
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InstrItinData<IIC_LdStLoad , [InstrStage<3, [SLU]>]>,
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InstrItinData<IIC_LdStLoadUpd , [InstrStage<3, [SLU]>]>,
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InstrItinData<IIC_LdStStore , [InstrStage<3, [SLU]>]>,
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InstrItinData<IIC_LdStStoreUpd, [InstrStage<3, [SLU]>]>,
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InstrItinData<IIC_LdStDSS , [InstrStage<3, [SLU]>]>,
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InstrItinData<IIC_LdStICBI , [InstrStage<3, [IU2]>]>,
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InstrItinData<IIC_LdStSTFD , [InstrStage<3, [SLU]>]>,
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InstrItinData<IIC_LdStSTFDU , [InstrStage<3, [SLU]>]>,
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InstrItinData<IIC_LdStLFD , [InstrStage<4, [SLU]>]>,
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InstrItinData<IIC_LdStLFDU , [InstrStage<4, [SLU]>]>,
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InstrItinData<IIC_LdStLHA , [InstrStage<3, [SLU]>]>,
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InstrItinData<IIC_LdStLHAU , [InstrStage<3, [SLU]>]>,
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InstrItinData<IIC_LdStLMW , [InstrStage<37, [SLU]>]>,
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InstrItinData<IIC_LdStLVecX , [InstrStage<3, [SLU]>]>,
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InstrItinData<IIC_LdStLWA , [InstrStage<3, [SLU]>]>,
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InstrItinData<IIC_LdStLWARX , [InstrStage<3, [SLU]>]>,
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InstrItinData<IIC_LdStSTD , [InstrStage<3, [SLU]>]>,
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InstrItinData<IIC_LdStSTDCX , [InstrStage<3, [SLU]>]>,
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InstrItinData<IIC_LdStSTDU , [InstrStage<3, [SLU]>]>,
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InstrItinData<IIC_LdStSTVEBX , [InstrStage<3, [SLU]>]>,
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InstrItinData<IIC_LdStSTWCX , [InstrStage<3, [SLU]>]>,
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InstrItinData<IIC_LdStSync , [InstrStage<35, [SLU]>]>,
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InstrItinData<IIC_SprISYNC , [InstrStage<0, [IU1, IU2, IU3, IU4]>]>,
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InstrItinData<IIC_SprMFSR , [InstrStage<4, [IU2]>]>,
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InstrItinData<IIC_SprMTMSR , [InstrStage<2, [IU2]>]>,
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InstrItinData<IIC_SprMTSR , [InstrStage<2, [IU2]>]>,
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InstrItinData<IIC_SprTLBSYNC , [InstrStage<3, [SLU]>]>,
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InstrItinData<IIC_SprMFCR , [InstrStage<2, [IU2]>]>,
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InstrItinData<IIC_SprMFMSR , [InstrStage<3, [IU2]>]>,
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InstrItinData<IIC_SprMFSPR , [InstrStage<4, [IU2]>]>,
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InstrItinData<IIC_SprMFTB , [InstrStage<5, [IU2]>]>,
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InstrItinData<IIC_SprMTSPR , [InstrStage<2, [IU2]>]>,
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InstrItinData<IIC_SprMTSRIN , [InstrStage<2, [IU2]>]>,
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InstrItinData<IIC_SprRFI , [InstrStage<1, [IU1, IU2, IU3, IU4]>]>,
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InstrItinData<IIC_SprSC , [InstrStage<0, [IU1, IU2, IU3, IU4]>]>,
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InstrItinData<IIC_FPGeneral , [InstrStage<5, [FPU1]>]>,
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InstrItinData<IIC_FPAddSub , [InstrStage<5, [FPU1]>]>,
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InstrItinData<IIC_FPCompare , [InstrStage<5, [FPU1]>]>,
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InstrItinData<IIC_FPDivD , [InstrStage<35, [FPU1]>]>,
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InstrItinData<IIC_FPDivS , [InstrStage<21, [FPU1]>]>,
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InstrItinData<IIC_FPFused , [InstrStage<5, [FPU1]>]>,
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InstrItinData<IIC_FPRes , [InstrStage<14, [FPU1]>]>,
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InstrItinData<IIC_VecGeneral , [InstrStage<1, [VIU1]>]>,
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InstrItinData<IIC_VecFP , [InstrStage<4, [VFPU]>]>,
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InstrItinData<IIC_VecFPCompare, [InstrStage<2, [VFPU]>]>,
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InstrItinData<IIC_VecComplex , [InstrStage<4, [VIU2]>]>,
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InstrItinData<IIC_VecPerm , [InstrStage<2, [VPU]>]>,
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InstrItinData<IIC_VecFPRound , [InstrStage<4, [VIU1]>]>,
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InstrItinData<IIC_VecVSL , [InstrStage<2, [VPU]>]>,
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InstrItinData<IIC_VecVSR , [InstrStage<2, [VPU]>]>
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]>;
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