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ca0f4dc4f0
This commit starts with a "git mv ARM64 AArch64" and continues out from there, renaming the C++ classes, intrinsics, and other target-local objects for consistency. "ARM64" test directories are also moved, and tests that began their life in ARM64 use an arm64 triple, those from AArch64 use an aarch64 triple. Both should be equivalent though. This finishes the AArch64 merge, and everyone should feel free to continue committing as normal now. llvm-svn: 209577
58 lines
1.8 KiB
LLVM
58 lines
1.8 KiB
LLVM
; RUN: llc < %s -verify-machineinstrs -mtriple=aarch64-none-linux-gnu -mattr=+neon | FileCheck %s
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; A vector TruncStore can not be selected.
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; Test a trunc IR and a vector store IR can be selected correctly.
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define void @truncStore.v2i64(<2 x i64> %a, <2 x i32>* %result) {
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; CHECK-LABEL: truncStore.v2i64:
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; CHECK: xtn v{{[0-9]+}}.2s, v{{[0-9]+}}.2d
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; CHECK: {{st1 { v[0-9]+.2s }|str d[0-9]+}}, [x{{[0-9]+|sp}}]
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%b = trunc <2 x i64> %a to <2 x i32>
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store <2 x i32> %b, <2 x i32>* %result
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ret void
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}
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define void @truncStore.v4i32(<4 x i32> %a, <4 x i16>* %result) {
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; CHECK-LABEL: truncStore.v4i32:
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; CHECK: xtn v{{[0-9]+}}.4h, v{{[0-9]+}}.4s
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; CHECK: {{st1 { v[0-9]+.4h }|str d[0-9]+}}, [x{{[0-9]+|sp}}]
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%b = trunc <4 x i32> %a to <4 x i16>
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store <4 x i16> %b, <4 x i16>* %result
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ret void
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}
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define void @truncStore.v8i16(<8 x i16> %a, <8 x i8>* %result) {
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; CHECK-LABEL: truncStore.v8i16:
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; CHECK: xtn v{{[0-9]+}}.8b, v{{[0-9]+}}.8h
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; CHECK: {{st1 { v[0-9]+.8b }|str d[0-9]+}}, [x{{[0-9]+|sp}}]
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%b = trunc <8 x i16> %a to <8 x i8>
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store <8 x i8> %b, <8 x i8>* %result
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ret void
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}
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; A vector LoadExt can not be selected.
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; Test a vector load IR and a sext/zext IR can be selected correctly.
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define <4 x i32> @loadSExt.v4i8(<4 x i8>* %ref) {
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; CHECK-LABEL: loadSExt.v4i8:
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; CHECK: ldrsb
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%a = load <4 x i8>* %ref
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%conv = sext <4 x i8> %a to <4 x i32>
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ret <4 x i32> %conv
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}
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define <4 x i32> @loadZExt.v4i8(<4 x i8>* %ref) {
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; CHECK-LABEL: loadZExt.v4i8:
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; CHECK: ldrb
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%a = load <4 x i8>* %ref
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%conv = zext <4 x i8> %a to <4 x i32>
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ret <4 x i32> %conv
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}
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define i32 @loadExt.i32(<4 x i8>* %ref) {
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; CHECK-LABEL: loadExt.i32:
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; CHECK: ldrb
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%a = load <4 x i8>* %ref
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%vecext = extractelement <4 x i8> %a, i32 0
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%conv = zext i8 %vecext to i32
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ret i32 %conv
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}
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