1
0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-11-26 04:32:44 +01:00
llvm-mirror/test/MC/AVR/inst-sbis.s
Ayke van Laethem 24ba078dcd [AVR] Implement disassembly support for I/O instructions
The in, out, and sbi/cbi family of instructions seem to require a custom
decoder. I'm not exactly sure why and would prefer to convince TableGen
to provide the correct decoders for these, but I can't seem to convince
it to do so. They simply disassemble without any operands.

Differential Revision: https://reviews.llvm.org/D74049
2020-06-10 20:55:47 +02:00

36 lines
1.0 KiB
ArmAsm

; RUN: llvm-mc -triple avr -show-encoding < %s | FileCheck %s
; RUN: llvm-mc -filetype=obj -triple avr < %s | llvm-objdump -d - | FileCheck -check-prefix=CHECK-INST %s
foo:
sbis 4, 3
sbis 6, 2
sbis 16, 5
sbis 0, 0
sbis 31, 0
sbis 0, 7
sbis 31, 7
sbis FOO+4, 7
; CHECK: sbis 4, 3 ; encoding: [0x23,0x9b]
; CHECK: sbis 6, 2 ; encoding: [0x32,0x9b]
; CHECK: sbis 16, 5 ; encoding: [0x85,0x9b]
; CHECK: sbis 0, 0 ; encoding: [0x00,0x9b]
; CHECK: sbis 31, 0 ; encoding: [0xf8,0x9b]
; CHECK: sbis 0, 7 ; encoding: [0x07,0x9b]
; CHECK: sbis 31, 7 ; encoding: [0xff,0x9b]
; CHECK: sbis FOO+4, 7 ; encoding: [0bAAAAA111,0x9b]
; CHECK: ; fixup A - offset: 0, value: FOO+4, kind: fixup_port5
; CHECK-INST: sbis 4, 3
; CHECK-INST: sbis 6, 2
; CHECK-INST: sbis 16, 5
; CHECK-INST: sbis 0, 0
; CHECK-INST: sbis 31, 0
; CHECK-INST: sbis 0, 7
; CHECK-INST: sbis 31, 7
; CHECK-INST: sbis 0, 7