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4e2def1840
TableGen had been nicely generating code to print a number of instructions using shorter aliases (and PowerPC has plenty of short mnemonics), but we were not calling it. For some of the aliases we support in the parser, TableGen can't infer the "inverse" alias relationship, so there is still more to do. Thus, after some hours of updating test cases... llvm-svn: 235616
40 lines
1.1 KiB
LLVM
40 lines
1.1 KiB
LLVM
; RUN: llc < %s -march=ppc32 | grep rotrw: | count 1
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; RUN: llc < %s -march=ppc32 | grep rotlw: | count 1
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; RUN: llc < %s -march=ppc32 | grep rotlwi: | count 1
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; RUN: llc < %s -march=ppc32 | grep rotrwi: | count 1
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define i32 @rotlw(i32 %x, i32 %sh) {
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entry:
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%tmp.7 = sub i32 32, %sh ; <i32> [#uses=1]
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%tmp.10 = lshr i32 %x, %tmp.7 ; <i32> [#uses=2]
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%tmp.4 = shl i32 %x, %sh ; <i32> [#uses=1]
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%tmp.12 = or i32 %tmp.10, %tmp.4 ; <i32> [#uses=1]
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ret i32 %tmp.12
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}
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define i32 @rotrw(i32 %x, i32 %sh) {
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entry:
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%tmp.3 = trunc i32 %sh to i8 ; <i8> [#uses=1]
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%tmp.4 = lshr i32 %x, %sh ; <i32> [#uses=2]
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%tmp.7 = sub i32 32, %sh ; <i32> [#uses=1]
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%tmp.10 = shl i32 %x, %tmp.7 ; <i32> [#uses=1]
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%tmp.12 = or i32 %tmp.4, %tmp.10 ; <i32> [#uses=1]
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ret i32 %tmp.12
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}
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define i32 @rotlwi(i32 %x) {
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entry:
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%tmp.7 = lshr i32 %x, 27 ; <i32> [#uses=2]
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%tmp.3 = shl i32 %x, 5 ; <i32> [#uses=1]
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%tmp.9 = or i32 %tmp.3, %tmp.7 ; <i32> [#uses=1]
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ret i32 %tmp.9
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}
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define i32 @rotrwi(i32 %x) {
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entry:
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%tmp.3 = lshr i32 %x, 5 ; <i32> [#uses=2]
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%tmp.7 = shl i32 %x, 27 ; <i32> [#uses=1]
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%tmp.9 = or i32 %tmp.3, %tmp.7 ; <i32> [#uses=1]
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ret i32 %tmp.9
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}
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