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418ea606d3
Summary: Re-used the IR-level debugify for the most part. The MIR-level code then adds locations to the MachineInstrs afterwards based on the LLVM-IR debug info. It's worth mentioning that the resulting locations make little sense as the range of line numbers used in a Function at the MIR level exceeds that of the equivelent IR level function. As such, MachineInstrs can appear to originate from outside the subprogram scope (and from other subprogram scopes). However, it doesn't seem worth worrying about as the source is imaginary anyway. There's a few high level goals this pass works towards: * We should be able to debugify our .ll/.mir in the lit tests without changing the checks and still pass them. I.e. Debug info should not change codegen. Combining this with a strip-debug pass should enable this. The main issue I ran into without the strip-debug pass was instructions with MMO's and checks on both the instruction and the MMO as the debug-location is between them. I currently have a simple hack in the MIRPrinter to resolve that but the more general solution is a proper strip-debug pass. * We should be able to test that GlobalISel does not lose debug info. I recently found that the legalizer can be unexpectedly lossy in seemingly simple cases (e.g. expanding one instr into many). I have a verifier (will be posted separately) that can be integrated with passes that use the observer interface and will catch location loss (it does not verify correctness, just that there's zero lossage). It is a little conservative as the line-0 locations that arise from conflicts do not track the conflicting locations but it can still catch a fair bit. Depends on D77439, D77438 Reviewers: aprantl, bogner, vsk Subscribers: mgorny, hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D77446
125 lines
5.2 KiB
C++
125 lines
5.2 KiB
C++
//===-- CodeGen.cpp -------------------------------------------------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements the common initialization routines for the
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// CodeGen library.
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//
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//===----------------------------------------------------------------------===//
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#include "llvm-c/Initialization.h"
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#include "llvm/InitializePasses.h"
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#include "llvm/PassRegistry.h"
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using namespace llvm;
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/// initializeCodeGen - Initialize all passes linked into the CodeGen library.
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void llvm::initializeCodeGen(PassRegistry &Registry) {
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initializeAtomicExpandPass(Registry);
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initializeBBSectionsPreparePass(Registry);
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initializeBranchFolderPassPass(Registry);
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initializeBranchRelaxationPass(Registry);
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initializeCFGuardLongjmpPass(Registry);
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initializeCFIInstrInserterPass(Registry);
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initializeCodeGenPreparePass(Registry);
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initializeDeadMachineInstructionElimPass(Registry);
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initializeDebugifyMachineModulePass(Registry);
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initializeDetectDeadLanesPass(Registry);
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initializeDwarfEHPreparePass(Registry);
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initializeEarlyIfConverterPass(Registry);
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initializeEarlyIfPredicatorPass(Registry);
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initializeEarlyMachineLICMPass(Registry);
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initializeEarlyTailDuplicatePass(Registry);
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initializeExpandMemCmpPassPass(Registry);
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initializeExpandPostRAPass(Registry);
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initializeFEntryInserterPass(Registry);
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initializeFinalizeISelPass(Registry);
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initializeFinalizeMachineBundlesPass(Registry);
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initializeFuncletLayoutPass(Registry);
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initializeGCMachineCodeAnalysisPass(Registry);
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initializeGCModuleInfoPass(Registry);
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initializeHardwareLoopsPass(Registry);
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initializeIfConverterPass(Registry);
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initializeImplicitNullChecksPass(Registry);
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initializeIndirectBrExpandPassPass(Registry);
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initializeInterleavedLoadCombinePass(Registry);
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initializeInterleavedAccessPass(Registry);
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initializeLiveDebugValuesPass(Registry);
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initializeLiveDebugVariablesPass(Registry);
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initializeLiveIntervalsPass(Registry);
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initializeLiveRangeShrinkPass(Registry);
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initializeLiveStacksPass(Registry);
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initializeLiveVariablesPass(Registry);
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initializeLocalStackSlotPassPass(Registry);
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initializeLowerIntrinsicsPass(Registry);
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initializeMIRCanonicalizerPass(Registry);
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initializeMIRNamerPass(Registry);
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initializeMachineBlockFrequencyInfoPass(Registry);
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initializeMachineBlockPlacementPass(Registry);
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initializeMachineBlockPlacementStatsPass(Registry);
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initializeMachineCSEPass(Registry);
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initializeMachineCombinerPass(Registry);
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initializeMachineCopyPropagationPass(Registry);
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initializeMachineDominatorTreePass(Registry);
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initializeMachineFunctionPrinterPassPass(Registry);
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initializeMachineLICMPass(Registry);
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initializeMachineLoopInfoPass(Registry);
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initializeMachineModuleInfoWrapperPassPass(Registry);
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initializeMachineOptimizationRemarkEmitterPassPass(Registry);
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initializeMachineOutlinerPass(Registry);
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initializeMachinePipelinerPass(Registry);
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initializeModuloScheduleTestPass(Registry);
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initializeMachinePostDominatorTreePass(Registry);
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initializeMachineRegionInfoPassPass(Registry);
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initializeMachineSchedulerPass(Registry);
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initializeMachineSinkingPass(Registry);
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initializeMachineVerifierPassPass(Registry);
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initializeOptimizePHIsPass(Registry);
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initializePEIPass(Registry);
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initializePHIEliminationPass(Registry);
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initializePatchableFunctionPass(Registry);
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initializePeepholeOptimizerPass(Registry);
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initializePostMachineSchedulerPass(Registry);
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initializePostRAHazardRecognizerPass(Registry);
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initializePostRAMachineSinkingPass(Registry);
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initializePostRASchedulerPass(Registry);
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initializePreISelIntrinsicLoweringLegacyPassPass(Registry);
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initializeProcessImplicitDefsPass(Registry);
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initializeRABasicPass(Registry);
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initializeRAGreedyPass(Registry);
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initializeRegAllocFastPass(Registry);
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initializeRegUsageInfoCollectorPass(Registry);
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initializeRegUsageInfoPropagationPass(Registry);
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initializeRegisterCoalescerPass(Registry);
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initializeRenameIndependentSubregsPass(Registry);
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initializeSafeStackLegacyPassPass(Registry);
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initializeScalarizeMaskedMemIntrinPass(Registry);
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initializeShrinkWrapPass(Registry);
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initializeSjLjEHPreparePass(Registry);
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initializeSlotIndexesPass(Registry);
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initializeStackColoringPass(Registry);
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initializeStackMapLivenessPass(Registry);
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initializeStackProtectorPass(Registry);
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initializeStackSlotColoringPass(Registry);
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initializeTailDuplicatePass(Registry);
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initializeTargetPassConfigPass(Registry);
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initializeTwoAddressInstructionPassPass(Registry);
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initializeTypePromotionPass(Registry);
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initializeUnpackMachineBundlesPass(Registry);
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initializeUnreachableBlockElimLegacyPassPass(Registry);
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initializeUnreachableMachineBlockElimPass(Registry);
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initializeVirtRegMapPass(Registry);
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initializeVirtRegRewriterPass(Registry);
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initializeWasmEHPreparePass(Registry);
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initializeWinEHPreparePass(Registry);
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initializeXRayInstrumentationPass(Registry);
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}
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void LLVMInitializeCodeGen(LLVMPassRegistryRef R) {
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initializeCodeGen(*unwrap(R));
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}
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