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https://github.com/RPCS3/llvm-mirror.git
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422c27e8aa
Allows preserving MachineMemOperands on intrinsics through selection. For reasons I don't understand, this is a static property of the pattern and the selector deliberately goes out of its way to drop if not present. Intrinsics already inherit from SDPatternOperator allowing them to be used directly in instruction patterns. SDPatternOperator has a list of SDNodeProperty, but you currently can't set them on the intrinsic. Without SDNPMemOperand, when the node is selected any memory operands are always dropped. Allowing setting this on the intrinsics avoids needing to introduce another equivalent target node just to have SDNPMemOperand set. llvm-svn: 321212
694 lines
26 KiB
C++
694 lines
26 KiB
C++
//===- CodeGenTarget.cpp - CodeGen Target Class Wrapper -------------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This class wraps target description classes used by the various code
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// generation TableGen backends. This makes it easier to access the data and
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// provides a single place that needs to check it for validity. All of these
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// classes abort on error conditions.
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//
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//===----------------------------------------------------------------------===//
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#include "CodeGenTarget.h"
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#include "CodeGenDAGPatterns.h"
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#include "CodeGenIntrinsics.h"
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#include "CodeGenSchedule.h"
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#include "llvm/ADT/STLExtras.h"
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#include "llvm/ADT/StringExtras.h"
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#include "llvm/Support/CommandLine.h"
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#include "llvm/TableGen/Error.h"
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#include "llvm/TableGen/Record.h"
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#include <algorithm>
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using namespace llvm;
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cl::OptionCategory AsmParserCat("Options for -gen-asm-parser");
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cl::OptionCategory AsmWriterCat("Options for -gen-asm-writer");
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static cl::opt<unsigned>
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AsmParserNum("asmparsernum", cl::init(0),
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cl::desc("Make -gen-asm-parser emit assembly parser #N"),
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cl::cat(AsmParserCat));
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static cl::opt<unsigned>
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AsmWriterNum("asmwriternum", cl::init(0),
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cl::desc("Make -gen-asm-writer emit assembly writer #N"),
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cl::cat(AsmWriterCat));
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/// getValueType - Return the MVT::SimpleValueType that the specified TableGen
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/// record corresponds to.
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MVT::SimpleValueType llvm::getValueType(Record *Rec) {
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return (MVT::SimpleValueType)Rec->getValueAsInt("Value");
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}
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StringRef llvm::getName(MVT::SimpleValueType T) {
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switch (T) {
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case MVT::Other: return "UNKNOWN";
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case MVT::iPTR: return "TLI.getPointerTy()";
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case MVT::iPTRAny: return "TLI.getPointerTy()";
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default: return getEnumName(T);
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}
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}
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StringRef llvm::getEnumName(MVT::SimpleValueType T) {
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switch (T) {
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case MVT::Other: return "MVT::Other";
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case MVT::i1: return "MVT::i1";
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case MVT::i8: return "MVT::i8";
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case MVT::i16: return "MVT::i16";
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case MVT::i32: return "MVT::i32";
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case MVT::i64: return "MVT::i64";
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case MVT::i128: return "MVT::i128";
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case MVT::Any: return "MVT::Any";
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case MVT::iAny: return "MVT::iAny";
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case MVT::fAny: return "MVT::fAny";
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case MVT::vAny: return "MVT::vAny";
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case MVT::f16: return "MVT::f16";
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case MVT::f32: return "MVT::f32";
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case MVT::f64: return "MVT::f64";
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case MVT::f80: return "MVT::f80";
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case MVT::f128: return "MVT::f128";
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case MVT::ppcf128: return "MVT::ppcf128";
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case MVT::x86mmx: return "MVT::x86mmx";
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case MVT::Glue: return "MVT::Glue";
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case MVT::isVoid: return "MVT::isVoid";
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case MVT::v1i1: return "MVT::v1i1";
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case MVT::v2i1: return "MVT::v2i1";
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case MVT::v4i1: return "MVT::v4i1";
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case MVT::v8i1: return "MVT::v8i1";
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case MVT::v16i1: return "MVT::v16i1";
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case MVT::v32i1: return "MVT::v32i1";
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case MVT::v64i1: return "MVT::v64i1";
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case MVT::v128i1: return "MVT::v128i1";
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case MVT::v512i1: return "MVT::v512i1";
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case MVT::v1024i1: return "MVT::v1024i1";
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case MVT::v1i8: return "MVT::v1i8";
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case MVT::v2i8: return "MVT::v2i8";
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case MVT::v4i8: return "MVT::v4i8";
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case MVT::v8i8: return "MVT::v8i8";
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case MVT::v16i8: return "MVT::v16i8";
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case MVT::v32i8: return "MVT::v32i8";
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case MVT::v64i8: return "MVT::v64i8";
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case MVT::v128i8: return "MVT::v128i8";
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case MVT::v256i8: return "MVT::v256i8";
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case MVT::v1i16: return "MVT::v1i16";
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case MVT::v2i16: return "MVT::v2i16";
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case MVT::v4i16: return "MVT::v4i16";
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case MVT::v8i16: return "MVT::v8i16";
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case MVT::v16i16: return "MVT::v16i16";
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case MVT::v32i16: return "MVT::v32i16";
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case MVT::v64i16: return "MVT::v64i16";
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case MVT::v128i16: return "MVT::v128i16";
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case MVT::v1i32: return "MVT::v1i32";
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case MVT::v2i32: return "MVT::v2i32";
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case MVT::v4i32: return "MVT::v4i32";
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case MVT::v8i32: return "MVT::v8i32";
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case MVT::v16i32: return "MVT::v16i32";
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case MVT::v32i32: return "MVT::v32i32";
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case MVT::v64i32: return "MVT::v64i32";
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case MVT::v1i64: return "MVT::v1i64";
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case MVT::v2i64: return "MVT::v2i64";
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case MVT::v4i64: return "MVT::v4i64";
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case MVT::v8i64: return "MVT::v8i64";
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case MVT::v16i64: return "MVT::v16i64";
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case MVT::v32i64: return "MVT::v32i64";
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case MVT::v1i128: return "MVT::v1i128";
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case MVT::v2f16: return "MVT::v2f16";
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case MVT::v4f16: return "MVT::v4f16";
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case MVT::v8f16: return "MVT::v8f16";
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case MVT::v1f32: return "MVT::v1f32";
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case MVT::v2f32: return "MVT::v2f32";
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case MVT::v4f32: return "MVT::v4f32";
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case MVT::v8f32: return "MVT::v8f32";
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case MVT::v16f32: return "MVT::v16f32";
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case MVT::v1f64: return "MVT::v1f64";
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case MVT::v2f64: return "MVT::v2f64";
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case MVT::v4f64: return "MVT::v4f64";
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case MVT::v8f64: return "MVT::v8f64";
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case MVT::nxv1i1: return "MVT::nxv1i1";
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case MVT::nxv2i1: return "MVT::nxv2i1";
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case MVT::nxv4i1: return "MVT::nxv4i1";
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case MVT::nxv8i1: return "MVT::nxv8i1";
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case MVT::nxv16i1: return "MVT::nxv16i1";
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case MVT::nxv32i1: return "MVT::nxv32i1";
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case MVT::nxv1i8: return "MVT::nxv1i8";
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case MVT::nxv2i8: return "MVT::nxv2i8";
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case MVT::nxv4i8: return "MVT::nxv4i8";
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case MVT::nxv8i8: return "MVT::nxv8i8";
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case MVT::nxv16i8: return "MVT::nxv16i8";
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case MVT::nxv32i8: return "MVT::nxv32i8";
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case MVT::nxv1i16: return "MVT::nxv1i16";
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case MVT::nxv2i16: return "MVT::nxv2i16";
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case MVT::nxv4i16: return "MVT::nxv4i16";
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case MVT::nxv8i16: return "MVT::nxv8i16";
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case MVT::nxv16i16: return "MVT::nxv16i16";
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case MVT::nxv32i16: return "MVT::nxv32i16";
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case MVT::nxv1i32: return "MVT::nxv1i32";
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case MVT::nxv2i32: return "MVT::nxv2i32";
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case MVT::nxv4i32: return "MVT::nxv4i32";
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case MVT::nxv8i32: return "MVT::nxv8i32";
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case MVT::nxv16i32: return "MVT::nxv16i32";
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case MVT::nxv1i64: return "MVT::nxv1i64";
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case MVT::nxv2i64: return "MVT::nxv2i64";
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case MVT::nxv4i64: return "MVT::nxv4i64";
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case MVT::nxv8i64: return "MVT::nxv8i64";
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case MVT::nxv16i64: return "MVT::nxv16i64";
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case MVT::nxv2f16: return "MVT::nxv2f16";
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case MVT::nxv4f16: return "MVT::nxv4f16";
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case MVT::nxv8f16: return "MVT::nxv8f16";
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case MVT::nxv1f32: return "MVT::nxv1f32";
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case MVT::nxv2f32: return "MVT::nxv2f32";
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case MVT::nxv4f32: return "MVT::nxv4f32";
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case MVT::nxv8f32: return "MVT::nxv8f32";
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case MVT::nxv16f32: return "MVT::nxv16f32";
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case MVT::nxv1f64: return "MVT::nxv1f64";
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case MVT::nxv2f64: return "MVT::nxv2f64";
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case MVT::nxv4f64: return "MVT::nxv4f64";
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case MVT::nxv8f64: return "MVT::nxv8f64";
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case MVT::token: return "MVT::token";
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case MVT::Metadata: return "MVT::Metadata";
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case MVT::iPTR: return "MVT::iPTR";
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case MVT::iPTRAny: return "MVT::iPTRAny";
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case MVT::Untyped: return "MVT::Untyped";
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default: llvm_unreachable("ILLEGAL VALUE TYPE!");
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}
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}
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/// getQualifiedName - Return the name of the specified record, with a
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/// namespace qualifier if the record contains one.
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///
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std::string llvm::getQualifiedName(const Record *R) {
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std::string Namespace;
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if (R->getValue("Namespace"))
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Namespace = R->getValueAsString("Namespace");
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if (Namespace.empty()) return R->getName();
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return Namespace + "::" + R->getName().str();
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}
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/// getTarget - Return the current instance of the Target class.
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///
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CodeGenTarget::CodeGenTarget(RecordKeeper &records)
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: Records(records), CGH(records) {
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std::vector<Record*> Targets = Records.getAllDerivedDefinitions("Target");
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if (Targets.size() == 0)
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PrintFatalError("ERROR: No 'Target' subclasses defined!");
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if (Targets.size() != 1)
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PrintFatalError("ERROR: Multiple subclasses of Target defined!");
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TargetRec = Targets[0];
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}
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CodeGenTarget::~CodeGenTarget() {
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}
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const StringRef CodeGenTarget::getName() const {
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return TargetRec->getName();
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}
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StringRef CodeGenTarget::getInstNamespace() const {
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for (const CodeGenInstruction *Inst : getInstructionsByEnumValue()) {
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// Make sure not to pick up "TargetOpcode" by accidentally getting
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// the namespace off the PHI instruction or something.
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if (Inst->Namespace != "TargetOpcode")
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return Inst->Namespace;
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}
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return "";
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}
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Record *CodeGenTarget::getInstructionSet() const {
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return TargetRec->getValueAsDef("InstructionSet");
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}
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/// getAsmParser - Return the AssemblyParser definition for this target.
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///
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Record *CodeGenTarget::getAsmParser() const {
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std::vector<Record*> LI = TargetRec->getValueAsListOfDefs("AssemblyParsers");
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if (AsmParserNum >= LI.size())
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PrintFatalError("Target does not have an AsmParser #" +
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Twine(AsmParserNum) + "!");
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return LI[AsmParserNum];
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}
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/// getAsmParserVariant - Return the AssmblyParserVariant definition for
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/// this target.
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///
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Record *CodeGenTarget::getAsmParserVariant(unsigned i) const {
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std::vector<Record*> LI =
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TargetRec->getValueAsListOfDefs("AssemblyParserVariants");
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if (i >= LI.size())
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PrintFatalError("Target does not have an AsmParserVariant #" + Twine(i) +
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"!");
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return LI[i];
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}
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/// getAsmParserVariantCount - Return the AssmblyParserVariant definition
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/// available for this target.
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///
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unsigned CodeGenTarget::getAsmParserVariantCount() const {
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std::vector<Record*> LI =
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TargetRec->getValueAsListOfDefs("AssemblyParserVariants");
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return LI.size();
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}
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/// getAsmWriter - Return the AssemblyWriter definition for this target.
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///
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Record *CodeGenTarget::getAsmWriter() const {
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std::vector<Record*> LI = TargetRec->getValueAsListOfDefs("AssemblyWriters");
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if (AsmWriterNum >= LI.size())
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PrintFatalError("Target does not have an AsmWriter #" +
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Twine(AsmWriterNum) + "!");
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return LI[AsmWriterNum];
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}
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CodeGenRegBank &CodeGenTarget::getRegBank() const {
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if (!RegBank)
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RegBank = llvm::make_unique<CodeGenRegBank>(Records, getHwModes());
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return *RegBank;
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}
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void CodeGenTarget::ReadRegAltNameIndices() const {
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RegAltNameIndices = Records.getAllDerivedDefinitions("RegAltNameIndex");
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std::sort(RegAltNameIndices.begin(), RegAltNameIndices.end(), LessRecord());
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}
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/// getRegisterByName - If there is a register with the specific AsmName,
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/// return it.
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const CodeGenRegister *CodeGenTarget::getRegisterByName(StringRef Name) const {
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const StringMap<CodeGenRegister*> &Regs = getRegBank().getRegistersByName();
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StringMap<CodeGenRegister*>::const_iterator I = Regs.find(Name);
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if (I == Regs.end())
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return nullptr;
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return I->second;
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}
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std::vector<ValueTypeByHwMode> CodeGenTarget::getRegisterVTs(Record *R)
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const {
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const CodeGenRegister *Reg = getRegBank().getReg(R);
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std::vector<ValueTypeByHwMode> Result;
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for (const auto &RC : getRegBank().getRegClasses()) {
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if (RC.contains(Reg)) {
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ArrayRef<ValueTypeByHwMode> InVTs = RC.getValueTypes();
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Result.insert(Result.end(), InVTs.begin(), InVTs.end());
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}
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}
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// Remove duplicates.
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std::sort(Result.begin(), Result.end());
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Result.erase(std::unique(Result.begin(), Result.end()), Result.end());
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return Result;
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}
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void CodeGenTarget::ReadLegalValueTypes() const {
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for (const auto &RC : getRegBank().getRegClasses())
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LegalValueTypes.insert(LegalValueTypes.end(), RC.VTs.begin(), RC.VTs.end());
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// Remove duplicates.
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std::sort(LegalValueTypes.begin(), LegalValueTypes.end());
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LegalValueTypes.erase(std::unique(LegalValueTypes.begin(),
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LegalValueTypes.end()),
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LegalValueTypes.end());
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}
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CodeGenSchedModels &CodeGenTarget::getSchedModels() const {
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if (!SchedModels)
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SchedModels = llvm::make_unique<CodeGenSchedModels>(Records, *this);
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return *SchedModels;
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}
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void CodeGenTarget::ReadInstructions() const {
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std::vector<Record*> Insts = Records.getAllDerivedDefinitions("Instruction");
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if (Insts.size() <= 2)
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PrintFatalError("No 'Instruction' subclasses defined!");
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// Parse the instructions defined in the .td file.
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for (unsigned i = 0, e = Insts.size(); i != e; ++i)
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Instructions[Insts[i]] = llvm::make_unique<CodeGenInstruction>(Insts[i]);
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}
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static const CodeGenInstruction *
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GetInstByName(const char *Name,
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const DenseMap<const Record*,
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std::unique_ptr<CodeGenInstruction>> &Insts,
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RecordKeeper &Records) {
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const Record *Rec = Records.getDef(Name);
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const auto I = Insts.find(Rec);
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if (!Rec || I == Insts.end())
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PrintFatalError(Twine("Could not find '") + Name + "' instruction!");
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return I->second.get();
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}
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/// \brief Return all of the instructions defined by the target, ordered by
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/// their enum value.
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void CodeGenTarget::ComputeInstrsByEnum() const {
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static const char *const FixedInstrs[] = {
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#define HANDLE_TARGET_OPCODE(OPC) #OPC,
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#include "llvm/CodeGen/TargetOpcodes.def"
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nullptr};
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const auto &Insts = getInstructions();
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for (const char *const *p = FixedInstrs; *p; ++p) {
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const CodeGenInstruction *Instr = GetInstByName(*p, Insts, Records);
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assert(Instr && "Missing target independent instruction");
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assert(Instr->Namespace == "TargetOpcode" && "Bad namespace");
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InstrsByEnum.push_back(Instr);
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}
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unsigned EndOfPredefines = InstrsByEnum.size();
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for (const auto &I : Insts) {
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const CodeGenInstruction *CGI = I.second.get();
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if (CGI->Namespace != "TargetOpcode")
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InstrsByEnum.push_back(CGI);
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}
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assert(InstrsByEnum.size() == Insts.size() && "Missing predefined instr");
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// All of the instructions are now in random order based on the map iteration.
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// Sort them by name.
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std::sort(InstrsByEnum.begin() + EndOfPredefines, InstrsByEnum.end(),
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[](const CodeGenInstruction *Rec1, const CodeGenInstruction *Rec2) {
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return Rec1->TheDef->getName() < Rec2->TheDef->getName();
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});
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}
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/// isLittleEndianEncoding - Return whether this target encodes its instruction
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/// in little-endian format, i.e. bits laid out in the order [0..n]
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///
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bool CodeGenTarget::isLittleEndianEncoding() const {
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return getInstructionSet()->getValueAsBit("isLittleEndianEncoding");
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}
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/// reverseBitsForLittleEndianEncoding - For little-endian instruction bit
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/// encodings, reverse the bit order of all instructions.
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void CodeGenTarget::reverseBitsForLittleEndianEncoding() {
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if (!isLittleEndianEncoding())
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return;
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std::vector<Record*> Insts = Records.getAllDerivedDefinitions("Instruction");
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for (Record *R : Insts) {
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if (R->getValueAsString("Namespace") == "TargetOpcode" ||
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R->getValueAsBit("isPseudo"))
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continue;
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BitsInit *BI = R->getValueAsBitsInit("Inst");
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unsigned numBits = BI->getNumBits();
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SmallVector<Init *, 16> NewBits(numBits);
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for (unsigned bit = 0, end = numBits / 2; bit != end; ++bit) {
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unsigned bitSwapIdx = numBits - bit - 1;
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Init *OrigBit = BI->getBit(bit);
|
|
Init *BitSwap = BI->getBit(bitSwapIdx);
|
|
NewBits[bit] = BitSwap;
|
|
NewBits[bitSwapIdx] = OrigBit;
|
|
}
|
|
if (numBits % 2) {
|
|
unsigned middle = (numBits + 1) / 2;
|
|
NewBits[middle] = BI->getBit(middle);
|
|
}
|
|
|
|
BitsInit *NewBI = BitsInit::get(NewBits);
|
|
|
|
// Update the bits in reversed order so that emitInstrOpBits will get the
|
|
// correct endianness.
|
|
R->getValue("Inst")->setValue(NewBI);
|
|
}
|
|
}
|
|
|
|
/// guessInstructionProperties - Return true if it's OK to guess instruction
|
|
/// properties instead of raising an error.
|
|
///
|
|
/// This is configurable as a temporary migration aid. It will eventually be
|
|
/// permanently false.
|
|
bool CodeGenTarget::guessInstructionProperties() const {
|
|
return getInstructionSet()->getValueAsBit("guessInstructionProperties");
|
|
}
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// ComplexPattern implementation
|
|
//
|
|
ComplexPattern::ComplexPattern(Record *R) {
|
|
Ty = ::getValueType(R->getValueAsDef("Ty"));
|
|
NumOperands = R->getValueAsInt("NumOperands");
|
|
SelectFunc = R->getValueAsString("SelectFunc");
|
|
RootNodes = R->getValueAsListOfDefs("RootNodes");
|
|
|
|
// FIXME: This is a hack to statically increase the priority of patterns which
|
|
// maps a sub-dag to a complex pattern. e.g. favors LEA over ADD. To get best
|
|
// possible pattern match we'll need to dynamically calculate the complexity
|
|
// of all patterns a dag can potentially map to.
|
|
int64_t RawComplexity = R->getValueAsInt("Complexity");
|
|
if (RawComplexity == -1)
|
|
Complexity = NumOperands * 3;
|
|
else
|
|
Complexity = RawComplexity;
|
|
|
|
// FIXME: Why is this different from parseSDPatternOperatorProperties?
|
|
// Parse the properties.
|
|
Properties = 0;
|
|
std::vector<Record*> PropList = R->getValueAsListOfDefs("Properties");
|
|
for (unsigned i = 0, e = PropList.size(); i != e; ++i)
|
|
if (PropList[i]->getName() == "SDNPHasChain") {
|
|
Properties |= 1 << SDNPHasChain;
|
|
} else if (PropList[i]->getName() == "SDNPOptInGlue") {
|
|
Properties |= 1 << SDNPOptInGlue;
|
|
} else if (PropList[i]->getName() == "SDNPMayStore") {
|
|
Properties |= 1 << SDNPMayStore;
|
|
} else if (PropList[i]->getName() == "SDNPMayLoad") {
|
|
Properties |= 1 << SDNPMayLoad;
|
|
} else if (PropList[i]->getName() == "SDNPSideEffect") {
|
|
Properties |= 1 << SDNPSideEffect;
|
|
} else if (PropList[i]->getName() == "SDNPMemOperand") {
|
|
Properties |= 1 << SDNPMemOperand;
|
|
} else if (PropList[i]->getName() == "SDNPVariadic") {
|
|
Properties |= 1 << SDNPVariadic;
|
|
} else if (PropList[i]->getName() == "SDNPWantRoot") {
|
|
Properties |= 1 << SDNPWantRoot;
|
|
} else if (PropList[i]->getName() == "SDNPWantParent") {
|
|
Properties |= 1 << SDNPWantParent;
|
|
} else {
|
|
PrintFatalError("Unsupported SD Node property '" +
|
|
PropList[i]->getName() + "' on ComplexPattern '" +
|
|
R->getName() + "'!");
|
|
}
|
|
}
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// CodeGenIntrinsic Implementation
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
CodeGenIntrinsicTable::CodeGenIntrinsicTable(const RecordKeeper &RC,
|
|
bool TargetOnly) {
|
|
std::vector<Record*> Defs = RC.getAllDerivedDefinitions("Intrinsic");
|
|
|
|
Intrinsics.reserve(Defs.size());
|
|
|
|
for (unsigned I = 0, e = Defs.size(); I != e; ++I) {
|
|
bool isTarget = Defs[I]->getValueAsBit("isTarget");
|
|
if (isTarget == TargetOnly)
|
|
Intrinsics.push_back(CodeGenIntrinsic(Defs[I]));
|
|
}
|
|
std::sort(Intrinsics.begin(), Intrinsics.end(),
|
|
[](const CodeGenIntrinsic &LHS, const CodeGenIntrinsic &RHS) {
|
|
return std::tie(LHS.TargetPrefix, LHS.Name) <
|
|
std::tie(RHS.TargetPrefix, RHS.Name);
|
|
});
|
|
Targets.push_back({"", 0, 0});
|
|
for (size_t I = 0, E = Intrinsics.size(); I < E; ++I)
|
|
if (Intrinsics[I].TargetPrefix != Targets.back().Name) {
|
|
Targets.back().Count = I - Targets.back().Offset;
|
|
Targets.push_back({Intrinsics[I].TargetPrefix, I, 0});
|
|
}
|
|
Targets.back().Count = Intrinsics.size() - Targets.back().Offset;
|
|
}
|
|
|
|
CodeGenIntrinsic::CodeGenIntrinsic(Record *R) {
|
|
TheDef = R;
|
|
std::string DefName = R->getName();
|
|
ModRef = ReadWriteMem;
|
|
Properties = 0;
|
|
isOverloaded = false;
|
|
isCommutative = false;
|
|
canThrow = false;
|
|
isNoReturn = false;
|
|
isNoDuplicate = false;
|
|
isConvergent = false;
|
|
isSpeculatable = false;
|
|
hasSideEffects = false;
|
|
|
|
if (DefName.size() <= 4 ||
|
|
std::string(DefName.begin(), DefName.begin() + 4) != "int_")
|
|
PrintFatalError("Intrinsic '" + DefName + "' does not start with 'int_'!");
|
|
|
|
EnumName = std::string(DefName.begin()+4, DefName.end());
|
|
|
|
if (R->getValue("GCCBuiltinName")) // Ignore a missing GCCBuiltinName field.
|
|
GCCBuiltinName = R->getValueAsString("GCCBuiltinName");
|
|
if (R->getValue("MSBuiltinName")) // Ignore a missing MSBuiltinName field.
|
|
MSBuiltinName = R->getValueAsString("MSBuiltinName");
|
|
|
|
TargetPrefix = R->getValueAsString("TargetPrefix");
|
|
Name = R->getValueAsString("LLVMName");
|
|
|
|
if (Name == "") {
|
|
// If an explicit name isn't specified, derive one from the DefName.
|
|
Name = "llvm.";
|
|
|
|
for (unsigned i = 0, e = EnumName.size(); i != e; ++i)
|
|
Name += (EnumName[i] == '_') ? '.' : EnumName[i];
|
|
} else {
|
|
// Verify it starts with "llvm.".
|
|
if (Name.size() <= 5 ||
|
|
std::string(Name.begin(), Name.begin() + 5) != "llvm.")
|
|
PrintFatalError("Intrinsic '" + DefName + "'s name does not start with 'llvm.'!");
|
|
}
|
|
|
|
// If TargetPrefix is specified, make sure that Name starts with
|
|
// "llvm.<targetprefix>.".
|
|
if (!TargetPrefix.empty()) {
|
|
if (Name.size() < 6+TargetPrefix.size() ||
|
|
std::string(Name.begin() + 5, Name.begin() + 6 + TargetPrefix.size())
|
|
!= (TargetPrefix + "."))
|
|
PrintFatalError("Intrinsic '" + DefName + "' does not start with 'llvm." +
|
|
TargetPrefix + ".'!");
|
|
}
|
|
|
|
// Parse the list of return types.
|
|
std::vector<MVT::SimpleValueType> OverloadedVTs;
|
|
ListInit *TypeList = R->getValueAsListInit("RetTypes");
|
|
for (unsigned i = 0, e = TypeList->size(); i != e; ++i) {
|
|
Record *TyEl = TypeList->getElementAsRecord(i);
|
|
assert(TyEl->isSubClassOf("LLVMType") && "Expected a type!");
|
|
MVT::SimpleValueType VT;
|
|
if (TyEl->isSubClassOf("LLVMMatchType")) {
|
|
unsigned MatchTy = TyEl->getValueAsInt("Number");
|
|
assert(MatchTy < OverloadedVTs.size() &&
|
|
"Invalid matching number!");
|
|
VT = OverloadedVTs[MatchTy];
|
|
// It only makes sense to use the extended and truncated vector element
|
|
// variants with iAny types; otherwise, if the intrinsic is not
|
|
// overloaded, all the types can be specified directly.
|
|
assert(((!TyEl->isSubClassOf("LLVMExtendedType") &&
|
|
!TyEl->isSubClassOf("LLVMTruncatedType")) ||
|
|
VT == MVT::iAny || VT == MVT::vAny) &&
|
|
"Expected iAny or vAny type");
|
|
} else {
|
|
VT = getValueType(TyEl->getValueAsDef("VT"));
|
|
}
|
|
if (MVT(VT).isOverloaded()) {
|
|
OverloadedVTs.push_back(VT);
|
|
isOverloaded = true;
|
|
}
|
|
|
|
// Reject invalid types.
|
|
if (VT == MVT::isVoid)
|
|
PrintFatalError("Intrinsic '" + DefName + " has void in result type list!");
|
|
|
|
IS.RetVTs.push_back(VT);
|
|
IS.RetTypeDefs.push_back(TyEl);
|
|
}
|
|
|
|
// Parse the list of parameter types.
|
|
TypeList = R->getValueAsListInit("ParamTypes");
|
|
for (unsigned i = 0, e = TypeList->size(); i != e; ++i) {
|
|
Record *TyEl = TypeList->getElementAsRecord(i);
|
|
assert(TyEl->isSubClassOf("LLVMType") && "Expected a type!");
|
|
MVT::SimpleValueType VT;
|
|
if (TyEl->isSubClassOf("LLVMMatchType")) {
|
|
unsigned MatchTy = TyEl->getValueAsInt("Number");
|
|
assert(MatchTy < OverloadedVTs.size() &&
|
|
"Invalid matching number!");
|
|
VT = OverloadedVTs[MatchTy];
|
|
// It only makes sense to use the extended and truncated vector element
|
|
// variants with iAny types; otherwise, if the intrinsic is not
|
|
// overloaded, all the types can be specified directly.
|
|
assert(((!TyEl->isSubClassOf("LLVMExtendedType") &&
|
|
!TyEl->isSubClassOf("LLVMTruncatedType") &&
|
|
!TyEl->isSubClassOf("LLVMVectorSameWidth")) ||
|
|
VT == MVT::iAny || VT == MVT::vAny) &&
|
|
"Expected iAny or vAny type");
|
|
} else
|
|
VT = getValueType(TyEl->getValueAsDef("VT"));
|
|
|
|
if (MVT(VT).isOverloaded()) {
|
|
OverloadedVTs.push_back(VT);
|
|
isOverloaded = true;
|
|
}
|
|
|
|
// Reject invalid types.
|
|
if (VT == MVT::isVoid && i != e-1 /*void at end means varargs*/)
|
|
PrintFatalError("Intrinsic '" + DefName + " has void in result type list!");
|
|
|
|
IS.ParamVTs.push_back(VT);
|
|
IS.ParamTypeDefs.push_back(TyEl);
|
|
}
|
|
|
|
// Parse the intrinsic properties.
|
|
ListInit *PropList = R->getValueAsListInit("IntrProperties");
|
|
for (unsigned i = 0, e = PropList->size(); i != e; ++i) {
|
|
Record *Property = PropList->getElementAsRecord(i);
|
|
assert(Property->isSubClassOf("IntrinsicProperty") &&
|
|
"Expected a property!");
|
|
|
|
if (Property->getName() == "IntrNoMem")
|
|
ModRef = NoMem;
|
|
else if (Property->getName() == "IntrReadMem")
|
|
ModRef = ModRefBehavior(ModRef & ~MR_Mod);
|
|
else if (Property->getName() == "IntrWriteMem")
|
|
ModRef = ModRefBehavior(ModRef & ~MR_Ref);
|
|
else if (Property->getName() == "IntrArgMemOnly")
|
|
ModRef = ModRefBehavior((ModRef & ~MR_Anywhere) | MR_ArgMem);
|
|
else if (Property->getName() == "IntrInaccessibleMemOnly")
|
|
ModRef = ModRefBehavior((ModRef & ~MR_Anywhere) | MR_InaccessibleMem);
|
|
else if (Property->getName() == "IntrInaccessibleMemOrArgMemOnly")
|
|
ModRef = ModRefBehavior((ModRef & ~MR_Anywhere) | MR_ArgMem |
|
|
MR_InaccessibleMem);
|
|
else if (Property->getName() == "Commutative")
|
|
isCommutative = true;
|
|
else if (Property->getName() == "Throws")
|
|
canThrow = true;
|
|
else if (Property->getName() == "IntrNoDuplicate")
|
|
isNoDuplicate = true;
|
|
else if (Property->getName() == "IntrConvergent")
|
|
isConvergent = true;
|
|
else if (Property->getName() == "IntrNoReturn")
|
|
isNoReturn = true;
|
|
else if (Property->getName() == "IntrSpeculatable")
|
|
isSpeculatable = true;
|
|
else if (Property->getName() == "IntrHasSideEffects")
|
|
hasSideEffects = true;
|
|
else if (Property->isSubClassOf("NoCapture")) {
|
|
unsigned ArgNo = Property->getValueAsInt("ArgNo");
|
|
ArgumentAttributes.push_back(std::make_pair(ArgNo, NoCapture));
|
|
} else if (Property->isSubClassOf("Returned")) {
|
|
unsigned ArgNo = Property->getValueAsInt("ArgNo");
|
|
ArgumentAttributes.push_back(std::make_pair(ArgNo, Returned));
|
|
} else if (Property->isSubClassOf("ReadOnly")) {
|
|
unsigned ArgNo = Property->getValueAsInt("ArgNo");
|
|
ArgumentAttributes.push_back(std::make_pair(ArgNo, ReadOnly));
|
|
} else if (Property->isSubClassOf("WriteOnly")) {
|
|
unsigned ArgNo = Property->getValueAsInt("ArgNo");
|
|
ArgumentAttributes.push_back(std::make_pair(ArgNo, WriteOnly));
|
|
} else if (Property->isSubClassOf("ReadNone")) {
|
|
unsigned ArgNo = Property->getValueAsInt("ArgNo");
|
|
ArgumentAttributes.push_back(std::make_pair(ArgNo, ReadNone));
|
|
} else
|
|
llvm_unreachable("Unknown property!");
|
|
}
|
|
|
|
// Also record the SDPatternOperator Properties.
|
|
Properties = parseSDPatternOperatorProperties(R);
|
|
|
|
// Sort the argument attributes for later benefit.
|
|
std::sort(ArgumentAttributes.begin(), ArgumentAttributes.end());
|
|
}
|
|
|