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to reflect the new license. We understand that people may be surprised that we're moving the header entirely to discuss the new license. We checked this carefully with the Foundation's lawyer and we believe this is the correct approach. Essentially, all code in the project is now made available by the LLVM project under our new license, so you will see that the license headers include that license only. Some of our contributors have contributed code under our old license, and accordingly, we have retained a copy of our old license notice in the top-level files in each project and repository. llvm-svn: 351636
129 lines
7.1 KiB
TableGen
129 lines
7.1 KiB
TableGen
//===-- PPCScheduleG5.td - PPC G5 Scheduling Definitions ---*- tablegen -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines the itinerary class data for the G5 (970) processor.
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//
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//===----------------------------------------------------------------------===//
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def G5_BPU : FuncUnit; // Branch unit
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def G5_SLU : FuncUnit; // Store/load unit
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def G5_SRU : FuncUnit; // special register unit
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def G5_IU1 : FuncUnit; // integer unit 1 (simple)
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def G5_IU2 : FuncUnit; // integer unit 2 (complex)
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def G5_FPU1 : FuncUnit; // floating point unit 1
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def G5_FPU2 : FuncUnit; // floating point unit 2
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def G5_VPU : FuncUnit; // vector permutation unit
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def G5_VIU1 : FuncUnit; // vector integer unit 1 (simple)
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def G5_VIU2 : FuncUnit; // vector integer unit 2 (complex)
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def G5_VFPU : FuncUnit; // vector floating point unit
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def G5Itineraries : ProcessorItineraries<
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[G5_IU1, G5_IU2, G5_SLU, G5_BPU, G5_FPU1, G5_FPU2,
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G5_VFPU, G5_VIU1, G5_VIU2, G5_VPU], [], [
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InstrItinData<IIC_IntSimple , [InstrStage<2, [G5_IU1, G5_IU2]>]>,
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InstrItinData<IIC_IntGeneral , [InstrStage<2, [G5_IU1, G5_IU2]>]>,
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InstrItinData<IIC_IntCompare , [InstrStage<3, [G5_IU1, G5_IU2]>]>,
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InstrItinData<IIC_IntDivD , [InstrStage<68, [G5_IU1]>]>,
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InstrItinData<IIC_IntDivW , [InstrStage<36, [G5_IU1]>]>,
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InstrItinData<IIC_IntMFFS , [InstrStage<6, [G5_IU2]>]>,
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InstrItinData<IIC_IntMFVSCR , [InstrStage<1, [G5_VFPU]>]>,
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InstrItinData<IIC_IntMTFSB0 , [InstrStage<6, [G5_FPU1, G5_FPU2]>]>,
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InstrItinData<IIC_IntMulHD , [InstrStage<7, [G5_IU1, G5_IU2]>]>,
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InstrItinData<IIC_IntMulHW , [InstrStage<5, [G5_IU1, G5_IU2]>]>,
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InstrItinData<IIC_IntMulHWU , [InstrStage<5, [G5_IU1, G5_IU2]>]>,
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InstrItinData<IIC_IntMulLI , [InstrStage<4, [G5_IU1, G5_IU2]>]>,
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InstrItinData<IIC_IntRFID , [InstrStage<1, [G5_IU2]>]>,
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InstrItinData<IIC_IntRotateD , [InstrStage<2, [G5_IU1, G5_IU2]>]>,
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InstrItinData<IIC_IntRotateDI , [InstrStage<2, [G5_IU1, G5_IU2]>]>,
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InstrItinData<IIC_IntRotate , [InstrStage<4, [G5_IU1, G5_IU2]>]>,
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InstrItinData<IIC_IntShift , [InstrStage<2, [G5_IU1, G5_IU2]>]>,
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InstrItinData<IIC_IntTrapD , [InstrStage<1, [G5_IU1, G5_IU2]>]>,
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InstrItinData<IIC_IntTrapW , [InstrStage<1, [G5_IU1, G5_IU2]>]>,
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InstrItinData<IIC_BrB , [InstrStage<1, [G5_BPU]>]>,
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InstrItinData<IIC_BrCR , [InstrStage<4, [G5_BPU]>]>,
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InstrItinData<IIC_BrMCR , [InstrStage<2, [G5_BPU]>]>,
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InstrItinData<IIC_BrMCRX , [InstrStage<3, [G5_BPU]>]>,
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InstrItinData<IIC_LdStDCBF , [InstrStage<3, [G5_SLU]>]>,
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InstrItinData<IIC_LdStLoad , [InstrStage<3, [G5_SLU]>]>,
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InstrItinData<IIC_LdStLoadUpd , [InstrStage<3, [G5_SLU]>]>,
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InstrItinData<IIC_LdStLoadUpdX, [InstrStage<3, [G5_SLU]>]>,
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InstrItinData<IIC_LdStStore , [InstrStage<3, [G5_SLU]>]>,
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InstrItinData<IIC_LdStDSS , [InstrStage<10, [G5_SLU]>]>,
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InstrItinData<IIC_LdStICBI , [InstrStage<40, [G5_SLU]>]>,
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InstrItinData<IIC_LdStSTFD , [InstrStage<4, [G5_SLU]>]>,
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InstrItinData<IIC_LdStSTFDU , [InstrStage<4, [G5_SLU]>]>,
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InstrItinData<IIC_LdStLD , [InstrStage<3, [G5_SLU]>]>,
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InstrItinData<IIC_LdStLDU , [InstrStage<3, [G5_SLU]>]>,
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InstrItinData<IIC_LdStLDUX , [InstrStage<3, [G5_SLU]>]>,
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InstrItinData<IIC_LdStLDARX , [InstrStage<11, [G5_SLU]>]>,
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InstrItinData<IIC_LdStLFD , [InstrStage<3, [G5_SLU]>]>,
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InstrItinData<IIC_LdStLFDU , [InstrStage<5, [G5_SLU]>]>,
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InstrItinData<IIC_LdStLFDUX , [InstrStage<5, [G5_SLU]>]>,
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InstrItinData<IIC_LdStLHA , [InstrStage<5, [G5_SLU]>]>,
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InstrItinData<IIC_LdStLHAU , [InstrStage<5, [G5_SLU]>]>,
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InstrItinData<IIC_LdStLHAUX , [InstrStage<5, [G5_SLU]>]>,
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InstrItinData<IIC_LdStLMW , [InstrStage<64, [G5_SLU]>]>,
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InstrItinData<IIC_LdStLVecX , [InstrStage<3, [G5_SLU]>]>,
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InstrItinData<IIC_LdStLWA , [InstrStage<5, [G5_SLU]>]>,
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InstrItinData<IIC_LdStLWARX , [InstrStage<11, [G5_SLU]>]>,
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InstrItinData<IIC_LdStSLBIA , [InstrStage<40, [G5_SLU]>]>, // needs work
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InstrItinData<IIC_LdStSLBIE , [InstrStage<2, [G5_SLU]>]>,
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InstrItinData<IIC_LdStSTD , [InstrStage<3, [G5_SLU]>]>,
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InstrItinData<IIC_LdStSTU , [InstrStage<3, [G5_SLU]>]>,
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InstrItinData<IIC_LdStSTUX , [InstrStage<3, [G5_SLU]>]>,
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InstrItinData<IIC_LdStSTDCX , [InstrStage<11, [G5_SLU]>]>,
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InstrItinData<IIC_LdStSTVEBX , [InstrStage<5, [G5_SLU]>]>,
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InstrItinData<IIC_LdStSTWCX , [InstrStage<11, [G5_SLU]>]>,
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InstrItinData<IIC_LdStSync , [InstrStage<35, [G5_SLU]>]>,
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InstrItinData<IIC_SprISYNC , [InstrStage<40, [G5_SLU]>]>, // needs work
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InstrItinData<IIC_SprMFSR , [InstrStage<3, [G5_SLU]>]>,
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InstrItinData<IIC_SprMTMSR , [InstrStage<3, [G5_SLU]>]>,
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InstrItinData<IIC_SprMTSR , [InstrStage<3, [G5_SLU]>]>,
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InstrItinData<IIC_SprTLBSYNC , [InstrStage<3, [G5_SLU]>]>,
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InstrItinData<IIC_SprMFCR , [InstrStage<2, [G5_IU2]>]>,
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InstrItinData<IIC_SprMFCRF , [InstrStage<2, [G5_IU2]>]>,
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InstrItinData<IIC_SprMFMSR , [InstrStage<3, [G5_IU2]>]>,
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InstrItinData<IIC_SprMFSPR , [InstrStage<3, [G5_IU2]>]>,
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InstrItinData<IIC_SprMFTB , [InstrStage<10, [G5_IU2]>]>,
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InstrItinData<IIC_SprMTSPR , [InstrStage<8, [G5_IU2]>]>,
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InstrItinData<IIC_SprSC , [InstrStage<1, [G5_IU2]>]>,
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InstrItinData<IIC_FPGeneral , [InstrStage<6, [G5_FPU1, G5_FPU2]>]>,
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InstrItinData<IIC_FPAddSub , [InstrStage<6, [G5_FPU1, G5_FPU2]>]>,
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InstrItinData<IIC_FPCompare , [InstrStage<8, [G5_FPU1, G5_FPU2]>]>,
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InstrItinData<IIC_FPDivD , [InstrStage<33, [G5_FPU1, G5_FPU2]>]>,
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InstrItinData<IIC_FPDivS , [InstrStage<33, [G5_FPU1, G5_FPU2]>]>,
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InstrItinData<IIC_FPFused , [InstrStage<6, [G5_FPU1, G5_FPU2]>]>,
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InstrItinData<IIC_FPRes , [InstrStage<6, [G5_FPU1, G5_FPU2]>]>,
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InstrItinData<IIC_FPSqrtD , [InstrStage<40, [G5_FPU1, G5_FPU2]>]>,
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InstrItinData<IIC_FPSqrtS , [InstrStage<40, [G5_FPU1, G5_FPU2]>]>,
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InstrItinData<IIC_VecGeneral , [InstrStage<2, [G5_VIU1]>]>,
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InstrItinData<IIC_VecFP , [InstrStage<8, [G5_VFPU]>]>,
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InstrItinData<IIC_VecFPCompare, [InstrStage<2, [G5_VFPU]>]>,
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InstrItinData<IIC_VecComplex , [InstrStage<5, [G5_VIU2]>]>,
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InstrItinData<IIC_VecPerm , [InstrStage<3, [G5_VPU]>]>,
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InstrItinData<IIC_VecFPRound , [InstrStage<8, [G5_VFPU]>]>,
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InstrItinData<IIC_VecVSL , [InstrStage<2, [G5_VIU1]>]>,
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InstrItinData<IIC_VecVSR , [InstrStage<3, [G5_VPU]>]>
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]>;
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// ===---------------------------------------------------------------------===//
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// G5 machine model for scheduling and other instruction cost heuristics.
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def G5Model : SchedMachineModel {
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let IssueWidth = 4; // 4 (non-branch) instructions are dispatched per cycle.
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let LoadLatency = 3; // Optimistic load latency assuming bypass.
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// This is overriden by OperandCycles if the
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// Itineraries are queried instead.
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let MispredictPenalty = 16;
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let CompleteModel = 0;
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let Itineraries = G5Itineraries;
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}
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