Craig Topper 428d8fda39 [X86] Model ADC/SBB with immediate 0 more accurately in the Haswell scheduler model ... Haswell and possibly Sandybridge have an optimization for ADC/SBB with immediate 0 to use a single uop flow. This only applies GR16/GR32/GR64 with an 8-bit immediate. It does not apply to GR8. It also does not apply to the implicit AX/EAX/RAX forms. Differential Revision: https://reviews.llvm.org/D59058 llvm-svn: 355635		2019-03-07 21:22:51 +00:00
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Analysis	[AMDGPU] Add support for 64 bit buffer atomic artihmetic instructions	2019-03-06 17:02:06 +00:00
Assembler
Bindings
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CodeGen	AMDHSA: Code object v3 updates	2019-03-07 19:58:29 +00:00
DebugInfo	[WebAssembly] Remove trailing whitespaces in tests (NFC)	2019-03-06 02:00:22 +00:00
Demangle
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Instrumentation	Fix invalid target triples in tests. (NFC)	2019-03-04 23:37:41 +00:00
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MC	AMDHSA: Code object v3 updates	2019-03-07 19:58:29 +00:00
Object	[llvm-readobj] Display section names for STT_SECTION symbols.	2019-03-01 17:31:32 +00:00
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Other	[PGO] Context sensitive PGO (part 4)	2019-03-06 19:31:37 +00:00
SafepointIRVerifier
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TableGen	TableGen: Allow lists to be concatenated through '#'	2019-03-05 17:16:07 +00:00
ThinLTO/X86	[ThinLTO] Use defined node and edge order when dumping DOT file	2019-02-26 07:38:21 +00:00
tools	[X86] Model ADC/SBB with immediate 0 more accurately in the Haswell scheduler model	2019-03-07 21:22:51 +00:00
Transforms	[InterleavedAccessAnalysis] Fix integer overflow in insertMember.	2019-03-07 17:50:16 +00:00
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