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7cd663b80c
Generally, the ISEL is expanded into if-then-else sequence, in some cases (like when the destination register is the same with the true or false value register), it may just be expanded into just the if or else sequence. llvm-svn: 292154
68 lines
2.2 KiB
LLVM
68 lines
2.2 KiB
LLVM
; RUN: llc -verify-machineinstrs -mcpu=pwr7 < %s | FileCheck %s
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; RUN: llc -verify-machineinstrs -O1 -mcpu=pwr7 < %s | FileCheck %s
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; RUN: llc -verify-machineinstrs -mcpu=pwr7 -ppc-gen-isel=false < %s | FileCheck --check-prefix=CHECK-NO-ISEL %s
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; RUN: llc -verify-machineinstrs -O1 -mcpu=pwr7 -ppc-gen-isel=false < %s | FileCheck --check-prefix=CHECK-NO-ISEL %s
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target datalayout = "E-m:e-i64:64-n32:64"
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target triple = "powerpc64-unknown-linux-gnu"
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define zeroext i1 @testi1(i1 zeroext %b1, i1 zeroext %b2) #0 {
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entry:
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%0 = tail call i8 asm "crand $0, $1, $2", "=^wc,^wc,^wc"(i1 %b1, i1 %b2) #0
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%1 = and i8 %0, 1
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%tobool3 = icmp ne i8 %1, 0
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ret i1 %tobool3
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; CHECK-LABEL: @testi1
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; CHECK-DAG: andi. {{[0-9]+}}, 3, 1
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; CHECK-DAG: li [[REG1:[0-9]+]], 0
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; CHECK-DAG: crmove [[REG2:[0-9]+]], 1
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; CHECK-DAG: andi. {{[0-9]+}}, 4, 1
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; CHECK-DAG: crand [[REG3:[0-9]+]], [[REG2]], 1
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; CHECK-DAG: li [[REG4:[0-9]+]], 1
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; CHECK: isel 3, [[REG4]], [[REG1]], [[REG3]]
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; CHECK-NO-ISEL-LABEL: @testi1
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; CHECK-NO-ISEL: bclr 12, 20, 0
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; CHECK-NO-ISEL: ori 3, 5, 0
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; CHECK-NO-ISEL-NEXT: blr
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; CHECK: blr
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}
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define signext i32 @testi32(i32 signext %b1, i32 signext %b2) #0 {
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entry:
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%0 = tail call i32 asm "crand $0, $1, $2", "=^wc,^wc,^wc"(i32 %b1, i32 %b2) #0
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ret i32 %0
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; The ABI sign_extend should combine with the any_extend from the asm result,
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; and the result will be 0 or -1. This highlights the fact that only the first
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; bit is meaningful.
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; CHECK-LABEL: @testi32
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; CHECK-DAG: andi. {{[0-9]+}}, 3, 1
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; CHECK-DAG: li [[REG1:[0-9]+]], 0
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; CHECK-DAG: crmove [[REG2:[0-9]+]], 1
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; CHECK-DAG: andi. {{[0-9]+}}, 4, 1
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; CHECK-DAG: crand [[REG3:[0-9]+]], [[REG2]], 1
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; CHECK-DAG: li [[REG4:[0-9]+]], -1
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; CHECK: isel 3, [[REG4]], [[REG1]], [[REG3]]
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; CHECK: blr
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}
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define zeroext i8 @testi8(i8 zeroext %b1, i8 zeroext %b2) #0 {
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entry:
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%0 = tail call i8 asm "crand $0, $1, $2", "=^wc,^wc,^wc"(i8 %b1, i8 %b2) #0
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ret i8 %0
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; CHECK-LABEL: @testi8
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; CHECK-DAG: andi. {{[0-9]+}}, 3, 1
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; CHECK-DAG: li [[REG1:[0-9]+]], 0
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; CHECK-DAG: crmove [[REG2:[0-9]+]], 1
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; CHECK-DAG: andi. {{[0-9]+}}, 4, 1
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; CHECK-DAG: crand [[REG3:[0-9]+]], [[REG2]], 1
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; CHECK-DAG: li [[REG4:[0-9]+]], 1
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; CHECK: isel 3, [[REG4]], [[REG1]], [[REG3]]
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; CHECK: blr
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}
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attributes #0 = { nounwind "target-features"="+crbits" }
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