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According to Power ISA V3.0 document, the first source operand of mtvsrdd is constant 0 if r0 is specified. So the corresponding register constraint should be g8rc_nox0. This bug caused wrong output generated by 401.bzip2 when -mcpu=power9 and fdo are specified. Differential Revision: https://reviews.llvm.org/D32880 llvm-svn: 302834
23 lines
750 B
LLVM
23 lines
750 B
LLVM
; RUN: llc -mcpu=pwr9 -ppc-vsr-nums-as-vr -mtriple=powerpc64le-unknown-unknown \
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; RUN: < %s | FileCheck %s
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; This test case checks r0 is used as constant 0 in instruction mtvsrdd.
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define <2 x i64> @const0(i64 %a) {
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%vecinit = insertelement <2 x i64> undef, i64 %a, i32 0
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%vecinit1 = insertelement <2 x i64> %vecinit, i64 0, i32 1
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ret <2 x i64> %vecinit1
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; CHECK-LABEL: const0
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; CHECK: mtvsrdd v2, 0, r3
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}
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define <2 x i64> @noconst0(i64* %a, i64* %b) {
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%1 = load i64, i64* %a, align 8
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%2 = load i64, i64* %b, align 8
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%vecinit = insertelement <2 x i64> undef, i64 %2, i32 0
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%vecinit1 = insertelement <2 x i64> %vecinit, i64 %1, i32 1
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ret <2 x i64> %vecinit1
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; CHECK-LABEL: noconst0
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; CHECK: mtvsrdd v2, {{r[0-9]+}}, {{r[0-9]+}}
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}
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