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db43217a24
Currently we have a number of tests that fail with -verify-machineinstrs. To detect this cases earlier we add the option to the testcases with the exception of tests that will currently fail with this option. PR 27456 keeps track of this failures. No code review, as discussed with Hal Finkel. llvm-svn: 277624
58 lines
1.9 KiB
LLVM
58 lines
1.9 KiB
LLVM
; RUN: llc -verify-machineinstrs -O1 < %s -march=ppc64 -mcpu=pwr7 | FileCheck %s
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target datalayout = "E-m:e-i64:64-n32:64"
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target triple = "powerpc64-unknown-linux-gnu"
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%struct.test = type { i64, [8 x i8] }
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%struct.pad = type { [8 x i64] }
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@gt = common global %struct.test zeroinitializer, align 16
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@gp = common global %struct.pad zeroinitializer, align 8
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define signext i32 @callee1(i32 signext %x, %struct.test* byval align 16 nocapture readnone %y, i32 signext %z) {
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entry:
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ret i32 %z
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}
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; CHECK-LABEL: @callee1
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; CHECK: mr 3, 7
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; CHECK: blr
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declare signext i32 @test1(i32 signext, %struct.test* byval align 16, i32 signext)
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define void @caller1(i32 signext %z) {
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entry:
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%call = tail call signext i32 @test1(i32 signext 0, %struct.test* byval align 16 @gt, i32 signext %z)
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ret void
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}
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; CHECK-LABEL: @caller1
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; CHECK: mr [[REG:[0-9]+]], 3
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; CHECK: mr 7, [[REG]]
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; CHECK: bl test1
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define i64 @callee2(%struct.pad* byval nocapture readnone %x, i32 signext %y, %struct.test* byval align 16 nocapture readonly %z) {
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entry:
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%x1 = getelementptr inbounds %struct.test, %struct.test* %z, i64 0, i32 0
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%0 = load i64, i64* %x1, align 16
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ret i64 %0
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}
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; CHECK-LABEL: @callee2
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; CHECK: ld 3, 128(1)
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; CHECK: blr
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declare i64 @test2(%struct.pad* byval, i32 signext, %struct.test* byval align 16)
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define void @caller2(i64 %z) {
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entry:
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%tmp = alloca %struct.test, align 16
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%.compoundliteral.sroa.0.0..sroa_idx = getelementptr inbounds %struct.test, %struct.test* %tmp, i64 0, i32 0
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store i64 %z, i64* %.compoundliteral.sroa.0.0..sroa_idx, align 16
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%call = call i64 @test2(%struct.pad* byval @gp, i32 signext 0, %struct.test* byval align 16 %tmp)
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ret void
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}
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; CHECK-LABEL: @caller2
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; CHECK: std 3, [[OFF:[0-9]+]](1)
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; CHECK: addi [[REG1:[0-9]+]], 1, [[OFF]]
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; CHECK: lxvw4x [[REG2:[0-9]+]], 0, [[REG1]]
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; CHECK: li [[REG3:[0-9]+]], 128
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; CHECK: stxvw4x 0, 1, [[REG3]]
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; CHECK: bl test2
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