mirror of
https://github.com/RPCS3/llvm-mirror.git
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4e4ba838d9
Re-apply r276044/r279124/r305516. Fixed a problem where we would refuse to place spills as the very first instruciton of a basic block and thus artifically increase pressure (test in test/CodeGen/PowerPC/scavenging.mir:spill_at_begin) This is a variant of scavengeRegister() that works for enterBasicBlockEnd()/backward(). The benefit of the backward mode is that it is not affected by incomplete kill flags. This patch also changes PrologEpilogInserter::doScavengeFrameVirtualRegs() to use the register scavenger in backwards mode. Differential Revision: http://reviews.llvm.org/D21885 llvm-svn: 305625
207 lines
5.0 KiB
YAML
207 lines
5.0 KiB
YAML
# RUN: llc -mtriple=ppc64-- -run-pass scavenger-test -verify-machineinstrs -o - %s | FileCheck %s
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---
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# CHECK-LABEL: name: noscav0
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name: noscav0
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tracksRegLiveness: true
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body: |
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bb.0:
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; CHECK: [[REG0:%r[0-9]+]] = LI 42
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; CHECK-NEXT: NOP implicit killed [[REG0]]
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%0 : gprc = LI 42
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NOP implicit %0
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; CHECK: [[REG1:%r[0-9]+]] = LI 42
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; CHECK-NEXT: NOP
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; CHECK-NEXT: NOP implicit [[REG1]]
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; CHECK-NEXT: NOP
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; CHECK-NEXT: NOP implicit killed [[REG1]]
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%1 : gprc = LI 42
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NOP
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NOP implicit %1
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NOP
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NOP implicit %1
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; CHECK: [[REG2:%r[0-9]+]] = LI 42
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; CHECK-NEXT: NOP implicit [[REG2]]
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%2 : gprc = LI 42
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NOP implicit %2
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%x0 = IMPLICIT_DEF
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%x1 = IMPLICIT_DEF
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%x2 = IMPLICIT_DEF
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%x3 = IMPLICIT_DEF
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%x4 = IMPLICIT_DEF
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%x27 = IMPLICIT_DEF
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%x28 = IMPLICIT_DEF
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%x29 = IMPLICIT_DEF
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%x30 = IMPLICIT_DEF
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; CHECK-NOT: %x0 = LI 42
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; CHECK-NOT: %x1 = LI 42
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; CHECK-NOT: %x2 = LI 42
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; CHECK-NOT: %x3 = LI 42
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; CHECK-NOT: %x4 = LI 42
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; CHECK-NOT: %x5 = LI 42
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; CHECK-NOT: %x27 = LI 42
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; CHECK-NOT: %x28 = LI 42
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; CHECK-NOT: %x29 = LI 42
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; CHECK-NOT: %x30 = LI 42
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; CHECK: [[REG3:%r[0-9]+]] = LI 42
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; CHECK-NEXT: %x5 = IMPLICIT_DEF
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; CHECK-NEXT: NOP implicit killed [[REG2]]
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; CHECK-NEXT: NOP implicit killed [[REG3]]
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%3 : gprc = LI 42
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%x5 = IMPLICIT_DEF
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NOP implicit %2
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NOP implicit %3
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NOP implicit %x0
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NOP implicit %x1
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NOP implicit %x2
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NOP implicit %x3
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NOP implicit %x4
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NOP implicit %x5
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NOP implicit %x27
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NOP implicit %x28
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NOP implicit %x29
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NOP implicit %x30
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...
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---
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# CHECK-LABEL: name: scav0
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name: scav0
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tracksRegLiveness: true
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stack:
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# variable-sized object should be a reason to reserve an emergency spillslot
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# in the RegScavenger
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- { id: 0, type: variable-sized, offset: -32, alignment: 1 }
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body: |
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bb.0:
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%x0 = IMPLICIT_DEF
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%x1 = IMPLICIT_DEF
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%x2 = IMPLICIT_DEF
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%x3 = IMPLICIT_DEF
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%x4 = IMPLICIT_DEF
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%x5 = IMPLICIT_DEF
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%x6 = IMPLICIT_DEF
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%x7 = IMPLICIT_DEF
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%x8 = IMPLICIT_DEF
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%x9 = IMPLICIT_DEF
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%x10 = IMPLICIT_DEF
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%x11 = IMPLICIT_DEF
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%x12 = IMPLICIT_DEF
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%x13 = IMPLICIT_DEF
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%x14 = IMPLICIT_DEF
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%x15 = IMPLICIT_DEF
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%x16 = IMPLICIT_DEF
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%x17 = IMPLICIT_DEF
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%x18 = IMPLICIT_DEF
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%x19 = IMPLICIT_DEF
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%x20 = IMPLICIT_DEF
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%x21 = IMPLICIT_DEF
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%x22 = IMPLICIT_DEF
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%x23 = IMPLICIT_DEF
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%x24 = IMPLICIT_DEF
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%x25 = IMPLICIT_DEF
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%x26 = IMPLICIT_DEF
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%x27 = IMPLICIT_DEF
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%x28 = IMPLICIT_DEF
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%x29 = IMPLICIT_DEF
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%x30 = IMPLICIT_DEF
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; CHECK: STD killed [[SPILLEDREG:%x[0-9]+]]
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; CHECK: [[SPILLEDREG]] = LI8 42
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; CHECK: NOP implicit killed [[SPILLEDREG]]
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; CHECK: [[SPILLEDREG]] = LD
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%0 : g8rc = LI8 42
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NOP implicit %0
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NOP implicit %x0
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NOP implicit %x1
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NOP implicit %x2
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NOP implicit %x3
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NOP implicit %x4
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NOP implicit %x5
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NOP implicit %x6
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NOP implicit %x7
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NOP implicit %x8
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NOP implicit %x9
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NOP implicit %x10
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NOP implicit %x11
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NOP implicit %x12
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NOP implicit %x13
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NOP implicit %x14
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NOP implicit %x15
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NOP implicit %x16
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NOP implicit %x17
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NOP implicit %x18
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NOP implicit %x19
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NOP implicit %x20
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NOP implicit %x21
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NOP implicit %x22
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NOP implicit %x23
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NOP implicit %x24
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NOP implicit %x25
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NOP implicit %x26
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NOP implicit %x27
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NOP implicit %x28
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NOP implicit %x29
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NOP implicit %x30
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...
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---
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# Check for bug where we would refuse to spill before the first instruction in a
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# block.
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# CHECK-LABEL: name: spill_at_begin
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# CHECK: bb.0:
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# CHECK: liveins:
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# CHECK: STD killed [[REG:%x[0-9]+]]{{.*}}(store 8 into %stack.{{[0-9]+}})
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# CHECK: [[REG]] = LIS8 0
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# CHECK: [[REG]] = ORI8 killed [[REG]], 48
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# CHECK: NOP implicit killed [[REG]]
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# CHEKC: [[REG]] = LD{{.*}}(load 8 from %stack.{{[0-9]+}})
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name: spill_at_begin
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tracksRegLiveness: true
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stack:
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# variable-sized object should be a reason to reserve an emergency spillslot
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# in the RegScavenger
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- { id: 0, type: variable-sized, offset: -32, alignment: 1 }
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body: |
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bb.0:
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liveins: %x0, %x1, %x2, %x3, %x4, %x5, %x6, %x7, %x8, %x9, %x10, %x11, %x12, %x13, %x14, %x15, %x16, %x17, %x18, %x19, %x20, %x21, %x22, %x23, %x24, %x25, %x26, %x27, %x28, %x29, %x30, %x31
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%0 : g8rc = LIS8 0
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%1 : g8rc = ORI8 %0, 48
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NOP implicit %1
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NOP implicit %x0
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NOP implicit %x1
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NOP implicit %x2
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NOP implicit %x3
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NOP implicit %x4
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NOP implicit %x5
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NOP implicit %x6
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NOP implicit %x7
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NOP implicit %x8
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NOP implicit %x9
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NOP implicit %x10
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NOP implicit %x11
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NOP implicit %x12
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NOP implicit %x13
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NOP implicit %x14
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NOP implicit %x15
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NOP implicit %x16
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NOP implicit %x17
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NOP implicit %x18
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NOP implicit %x19
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NOP implicit %x20
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NOP implicit %x21
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NOP implicit %x22
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NOP implicit %x23
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NOP implicit %x24
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NOP implicit %x25
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NOP implicit %x26
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NOP implicit %x27
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NOP implicit %x28
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NOP implicit %x29
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NOP implicit %x30
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NOP implicit %x31
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...
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