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9792b09ed3
This is essentially a recommit of r285893, but with a correctness fix. The problem of the original commit was that this: bic r5, r7, #31 cbz r5, .LBB2_10 got rewritten into: lsrs r5, r7, #5 beq .LBB2_10 The result in destination register r5 is not the same and this is incorrect when r5 is not dead. So this fix includes checking the uses of the AND destination register. And also, compared to the original commit, some regression tests didn't need changing anymore because of this extra check. For completeness, this was the original commit message: For the common pattern (CMPZ (AND x, #bitmask), #0), we can do some more efficient instruction selection if the bitmask is one consecutive sequence of set bits (32 - clz(bm) - ctz(bm) == popcount(bm)). 1) If the bitmask touches the LSB, then we can remove all the upper bits and set the flags by doing one LSLS. 2) If the bitmask touches the MSB, then we can remove all the lower bits and set the flags with one LSRS. 3) If the bitmask has popcount == 1 (only one set bit), we can shift that bit into the sign bit with one LSLS and change the condition query from NE/EQ to MI/PL (we could also implement this by shifting into the carry bit and branching on BCC/BCS). 4) Otherwise, we can emit a sequence of LSLS+LSRS to remove the upper and lower zero bits of the mask. 1-3 require only one 16-bit instruction and can elide the CMP. 4 requires two 16-bit instructions but can elide the CMP and doesn't require materializing a complex immediate, so is also a win. Differential Revision: https://reviews.llvm.org/D27761 llvm-svn: 289794
72 lines
1.3 KiB
LLVM
72 lines
1.3 KiB
LLVM
; RUN: llc -mtriple=thumbv7m-linux-gnu < %s | FileCheck %s --check-prefix=CHECK --check-prefix=T2
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; RUN: llc -mtriple=thumbv6m-linux-gnu < %s | FileCheck %s --check-prefix=CHECK --check-prefix=T1
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; CHECK-LABEL: single_bit:
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; CHECK: lsls r0, r0, #23
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; T2-NEXT: mov
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; T2-NEXT: it
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; T1-NEXT: bmi
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define i32 @single_bit(i32 %p) {
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%a = and i32 %p, 256
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%b = icmp eq i32 %a, 0
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br i1 %b, label %true, label %false
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true:
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ret i32 1
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false:
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ret i32 2
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}
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; CHECK-LABEL: multi_bit_lsb_ubfx:
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; CHECK: lsls r0, r0, #24
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; T2-NEXT: mov
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; T2-NEXT: it
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; T1-NEXT: beq
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define i32 @multi_bit_lsb_ubfx(i32 %p) {
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%a = and i32 %p, 255
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%b = icmp eq i32 %a, 0
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br i1 %b, label %true, label %false
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true:
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ret i32 1
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false:
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ret i32 2
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}
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; CHECK-LABEL: multi_bit_msb:
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; CHECK: lsrs r0, r0, #24
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; T2-NEXT: mov
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; T2-NEXT: it
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; T1-NEXT: beq
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define i32 @multi_bit_msb(i32 %p) {
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%a = and i32 %p, 4278190080 ; 0xff000000
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%b = icmp eq i32 %a, 0
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br i1 %b, label %true, label %false
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true:
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ret i32 1
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false:
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ret i32 2
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}
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; CHECK-LABEL: multi_bit_nosb:
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; T1: lsls r0, r0, #8
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; T1-NEXT: lsrs r0, r0, #24
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; T2: tst.w
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; T2-NEXT: it
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; T1-NEXT: beq
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define i32 @multi_bit_nosb(i32 %p) {
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%a = and i32 %p, 16711680 ; 0x00ff0000
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%b = icmp eq i32 %a, 0
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br i1 %b, label %true, label %false
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true:
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ret i32 1
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false:
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ret i32 2
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}
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