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42e36608f0
Previously print+verify passes were added in a very unsystematic way, which is annoying when debugging as you miss intermediate steps and allows bugs to stay unnotice when no verification is performed. To make this change practical I added the possibility to explicitely disable verification. I used this option on all places where no verification was performed previously (because alot of places actually don't pass the MachineVerifier). In the long term these problems should be fixed properly and verification enabled after each pass. I'll enable some more verification in subsequent commits. llvm-svn: 224042
294 lines
11 KiB
C++
294 lines
11 KiB
C++
//===-- ARMTargetMachine.cpp - Define TargetMachine for ARM ---------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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//
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//===----------------------------------------------------------------------===//
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#include "ARM.h"
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#include "ARMTargetMachine.h"
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#include "ARMFrameLowering.h"
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#include "ARMTargetObjectFile.h"
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#include "llvm/CodeGen/Passes.h"
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#include "llvm/IR/Function.h"
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#include "llvm/MC/MCAsmInfo.h"
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#include "llvm/PassManager.h"
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#include "llvm/Support/CommandLine.h"
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#include "llvm/Support/FormattedStream.h"
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#include "llvm/Support/TargetRegistry.h"
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#include "llvm/Target/TargetOptions.h"
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#include "llvm/Transforms/Scalar.h"
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using namespace llvm;
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static cl::opt<bool>
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DisableA15SDOptimization("disable-a15-sd-optimization", cl::Hidden,
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cl::desc("Inhibit optimization of S->D register accesses on A15"),
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cl::init(false));
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static cl::opt<bool>
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EnableAtomicTidy("arm-atomic-cfg-tidy", cl::Hidden,
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cl::desc("Run SimplifyCFG after expanding atomic operations"
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" to make use of cmpxchg flow-based information"),
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cl::init(true));
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extern "C" void LLVMInitializeARMTarget() {
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// Register the target.
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RegisterTargetMachine<ARMLETargetMachine> X(TheARMLETarget);
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RegisterTargetMachine<ARMBETargetMachine> Y(TheARMBETarget);
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RegisterTargetMachine<ThumbLETargetMachine> A(TheThumbLETarget);
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RegisterTargetMachine<ThumbBETargetMachine> B(TheThumbBETarget);
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}
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static std::unique_ptr<TargetLoweringObjectFile> createTLOF(const Triple &TT) {
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if (TT.isOSBinFormatMachO())
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return make_unique<TargetLoweringObjectFileMachO>();
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if (TT.isOSWindows())
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return make_unique<TargetLoweringObjectFileCOFF>();
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return make_unique<ARMElfTargetObjectFile>();
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}
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/// TargetMachine ctor - Create an ARM architecture model.
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///
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ARMBaseTargetMachine::ARMBaseTargetMachine(const Target &T, StringRef TT,
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StringRef CPU, StringRef FS,
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const TargetOptions &Options,
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Reloc::Model RM, CodeModel::Model CM,
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CodeGenOpt::Level OL, bool isLittle)
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: LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
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TLOF(createTLOF(Triple(getTargetTriple()))),
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Subtarget(TT, CPU, FS, *this, isLittle), isLittle(isLittle) {
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// Default to triple-appropriate float ABI
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if (Options.FloatABIType == FloatABI::Default)
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this->Options.FloatABIType =
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Subtarget.isTargetHardFloat() ? FloatABI::Hard : FloatABI::Soft;
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}
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ARMBaseTargetMachine::~ARMBaseTargetMachine() {}
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const ARMSubtarget *
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ARMBaseTargetMachine::getSubtargetImpl(const Function &F) const {
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AttributeSet FnAttrs = F.getAttributes();
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Attribute CPUAttr =
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FnAttrs.getAttribute(AttributeSet::FunctionIndex, "target-cpu");
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Attribute FSAttr =
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FnAttrs.getAttribute(AttributeSet::FunctionIndex, "target-features");
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std::string CPU = !CPUAttr.hasAttribute(Attribute::None)
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? CPUAttr.getValueAsString().str()
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: TargetCPU;
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std::string FS = !FSAttr.hasAttribute(Attribute::None)
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? FSAttr.getValueAsString().str()
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: TargetFS;
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// FIXME: This is related to the code below to reset the target options,
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// we need to know whether or not the soft float flag is set on the
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// function before we can generate a subtarget. We also need to use
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// it as a key for the subtarget since that can be the only difference
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// between two functions.
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Attribute SFAttr =
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FnAttrs.getAttribute(AttributeSet::FunctionIndex, "use-soft-float");
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bool SoftFloat = !SFAttr.hasAttribute(Attribute::None)
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? SFAttr.getValueAsString() == "true"
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: Options.UseSoftFloat;
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auto &I = SubtargetMap[CPU + FS + (SoftFloat ? "use-soft-float=true"
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: "use-soft-float=false")];
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if (!I) {
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// This needs to be done before we create a new subtarget since any
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// creation will depend on the TM and the code generation flags on the
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// function that reside in TargetOptions.
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resetTargetOptions(F);
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I = llvm::make_unique<ARMSubtarget>(TargetTriple, CPU, FS, *this, isLittle);
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}
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return I.get();
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}
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void ARMBaseTargetMachine::addAnalysisPasses(PassManagerBase &PM) {
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// Add first the target-independent BasicTTI pass, then our ARM pass. This
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// allows the ARM pass to delegate to the target independent layer when
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// appropriate.
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PM.add(createBasicTargetTransformInfoPass(this));
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PM.add(createARMTargetTransformInfoPass(this));
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}
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void ARMTargetMachine::anchor() { }
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ARMTargetMachine::ARMTargetMachine(const Target &T, StringRef TT, StringRef CPU,
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StringRef FS, const TargetOptions &Options,
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Reloc::Model RM, CodeModel::Model CM,
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CodeGenOpt::Level OL, bool isLittle)
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: ARMBaseTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, isLittle) {
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initAsmInfo();
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if (!Subtarget.hasARMOps())
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report_fatal_error("CPU: '" + Subtarget.getCPUString() + "' does not "
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"support ARM mode execution!");
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}
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void ARMLETargetMachine::anchor() { }
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ARMLETargetMachine::ARMLETargetMachine(const Target &T, StringRef TT,
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StringRef CPU, StringRef FS,
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const TargetOptions &Options,
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Reloc::Model RM, CodeModel::Model CM,
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CodeGenOpt::Level OL)
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: ARMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {}
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void ARMBETargetMachine::anchor() { }
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ARMBETargetMachine::ARMBETargetMachine(const Target &T, StringRef TT,
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StringRef CPU, StringRef FS,
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const TargetOptions &Options,
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Reloc::Model RM, CodeModel::Model CM,
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CodeGenOpt::Level OL)
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: ARMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {}
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void ThumbTargetMachine::anchor() { }
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ThumbTargetMachine::ThumbTargetMachine(const Target &T, StringRef TT,
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StringRef CPU, StringRef FS,
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const TargetOptions &Options,
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Reloc::Model RM, CodeModel::Model CM,
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CodeGenOpt::Level OL, bool isLittle)
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: ARMBaseTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL,
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isLittle) {
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initAsmInfo();
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}
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void ThumbLETargetMachine::anchor() { }
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ThumbLETargetMachine::ThumbLETargetMachine(const Target &T, StringRef TT,
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StringRef CPU, StringRef FS,
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const TargetOptions &Options,
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Reloc::Model RM, CodeModel::Model CM,
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CodeGenOpt::Level OL)
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: ThumbTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {}
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void ThumbBETargetMachine::anchor() { }
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ThumbBETargetMachine::ThumbBETargetMachine(const Target &T, StringRef TT,
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StringRef CPU, StringRef FS,
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const TargetOptions &Options,
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Reloc::Model RM, CodeModel::Model CM,
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CodeGenOpt::Level OL)
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: ThumbTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {}
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namespace {
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/// ARM Code Generator Pass Configuration Options.
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class ARMPassConfig : public TargetPassConfig {
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public:
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ARMPassConfig(ARMBaseTargetMachine *TM, PassManagerBase &PM)
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: TargetPassConfig(TM, PM) {}
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ARMBaseTargetMachine &getARMTargetMachine() const {
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return getTM<ARMBaseTargetMachine>();
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}
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const ARMSubtarget &getARMSubtarget() const {
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return *getARMTargetMachine().getSubtargetImpl();
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}
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void addIRPasses() override;
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bool addPreISel() override;
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bool addInstSelector() override;
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void addPreRegAlloc() override;
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void addPreSched2() override;
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void addPreEmitPass() override;
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};
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} // namespace
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TargetPassConfig *ARMBaseTargetMachine::createPassConfig(PassManagerBase &PM) {
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return new ARMPassConfig(this, PM);
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}
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void ARMPassConfig::addIRPasses() {
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if (TM->Options.ThreadModel == ThreadModel::Single)
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addPass(createLowerAtomicPass());
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else
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addPass(createAtomicExpandPass(TM));
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// Cmpxchg instructions are often used with a subsequent comparison to
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// determine whether it succeeded. We can exploit existing control-flow in
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// ldrex/strex loops to simplify this, but it needs tidying up.
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const ARMSubtarget *Subtarget = &getARMSubtarget();
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if (Subtarget->hasAnyDataBarrier() && !Subtarget->isThumb1Only())
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if (TM->getOptLevel() != CodeGenOpt::None && EnableAtomicTidy)
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addPass(createCFGSimplificationPass());
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TargetPassConfig::addIRPasses();
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}
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bool ARMPassConfig::addPreISel() {
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if (TM->getOptLevel() != CodeGenOpt::None)
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addPass(createGlobalMergePass(TM));
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return false;
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}
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bool ARMPassConfig::addInstSelector() {
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addPass(createARMISelDag(getARMTargetMachine(), getOptLevel()));
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const ARMSubtarget *Subtarget = &getARMSubtarget();
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if (Subtarget->isTargetELF() && !Subtarget->isThumb1Only() &&
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TM->Options.EnableFastISel)
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addPass(createARMGlobalBaseRegPass());
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return false;
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}
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void ARMPassConfig::addPreRegAlloc() {
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if (getOptLevel() != CodeGenOpt::None)
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addPass(createARMLoadStoreOptimizationPass(true), false);
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if (getOptLevel() != CodeGenOpt::None && getARMSubtarget().isCortexA9())
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addPass(createMLxExpansionPass(), false);
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// Since the A15SDOptimizer pass can insert VDUP instructions, it can only be
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// enabled when NEON is available.
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if (getOptLevel() != CodeGenOpt::None && getARMSubtarget().isCortexA15() &&
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getARMSubtarget().hasNEON() && !DisableA15SDOptimization) {
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addPass(createA15SDOptimizerPass());
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}
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}
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void ARMPassConfig::addPreSched2() {
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if (getOptLevel() != CodeGenOpt::None) {
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addPass(createARMLoadStoreOptimizationPass(), false);
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if (getARMSubtarget().hasNEON())
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addPass(createExecutionDependencyFixPass(&ARM::DPRRegClass), false);
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}
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// Expand some pseudo instructions into multiple instructions to allow
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// proper scheduling.
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addPass(createARMExpandPseudoPass(), false);
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if (getOptLevel() != CodeGenOpt::None) {
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if (!getARMSubtarget().isThumb1Only()) {
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// in v8, IfConversion depends on Thumb instruction widths
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if (getARMSubtarget().restrictIT() &&
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!getARMSubtarget().prefers32BitThumb())
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addPass(createThumb2SizeReductionPass(), false);
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addPass(&IfConverterID, false);
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}
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}
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if (getARMSubtarget().isThumb2())
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addPass(createThumb2ITBlockPass());
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}
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void ARMPassConfig::addPreEmitPass() {
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if (getARMSubtarget().isThumb2()) {
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if (!getARMSubtarget().prefers32BitThumb())
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addPass(createThumb2SizeReductionPass(), false);
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// Constant island pass work on unbundled instructions.
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addPass(&UnpackMachineBundlesID, false);
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}
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addPass(createARMOptimizeBarriersPass(), false);
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addPass(createARMConstantIslandPass());
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}
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