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32c979f9e1
r186399 aggressively used the RISBG instruction for immediate ANDs, both because it can handle some values that AND IMMEDIATE can't, and because it allows the destination register to be different from the source. I realized later while implementing the distinct-ops support that it would be better to leave the choice up to convertToThreeAddress() instead. The AND IMMEDIATE form is shorter and is less likely to be cracked. This is a problem for 32-bit ANDs because we assume that all 32-bit operations will leave the high word untouched, whereas RISBG used in this way will either clear the high word or copy it from the source register. The patch uses the z196 instruction RISBLG for this instead. This means that z10 will be restricted to NILL, NILH and NILF for 32-bit ANDs, but I think that should be OK for now. Although we're using z10 as the base architecture, the optimization work is going to be focused more on z196 and zEC12. llvm-svn: 187492
231 lines
5.6 KiB
LLVM
231 lines
5.6 KiB
LLVM
; Test insertions of memory into the low byte of an i64.
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;
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; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
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; Check a plain insertion with (or (and ... -0xff) (zext (load ....))).
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; The whole sequence can be performed by IC.
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define i64 @f1(i64 %orig, i8 *%ptr) {
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; CHECK-LABEL: f1:
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; CHECK-NOT: ni
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; CHECK: ic %r2, 0(%r3)
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; CHECK: br %r14
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%val = load i8 *%ptr
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%ptr2 = zext i8 %val to i64
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%ptr1 = and i64 %orig, -256
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%or = or i64 %ptr1, %ptr2
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ret i64 %or
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}
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; Like f1, but with the operands reversed.
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define i64 @f2(i64 %orig, i8 *%ptr) {
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; CHECK-LABEL: f2:
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; CHECK-NOT: ni
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; CHECK: ic %r2, 0(%r3)
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; CHECK: br %r14
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%val = load i8 *%ptr
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%ptr2 = zext i8 %val to i64
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%ptr1 = and i64 %orig, -256
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%or = or i64 %ptr2, %ptr1
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ret i64 %or
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}
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; Check a case where more bits than lower 8 are masked out of the
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; register value. We can use IC but must keep the original mask.
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define i64 @f3(i64 %orig, i8 *%ptr) {
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; CHECK-LABEL: f3:
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; CHECK: nill %r2, 65024
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; CHECK: ic %r2, 0(%r3)
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; CHECK: br %r14
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%val = load i8 *%ptr
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%ptr2 = zext i8 %val to i64
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%ptr1 = and i64 %orig, -512
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%or = or i64 %ptr1, %ptr2
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ret i64 %or
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}
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; Like f3, but with the operands reversed.
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define i64 @f4(i64 %orig, i8 *%ptr) {
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; CHECK-LABEL: f4:
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; CHECK: nill %r2, 65024
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; CHECK: ic %r2, 0(%r3)
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; CHECK: br %r14
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%val = load i8 *%ptr
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%ptr2 = zext i8 %val to i64
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%ptr1 = and i64 %orig, -512
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%or = or i64 %ptr2, %ptr1
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ret i64 %or
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}
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; Check a case where the low 8 bits are cleared by a shift left.
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define i64 @f5(i64 %orig, i8 *%ptr) {
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; CHECK-LABEL: f5:
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; CHECK: sllg %r2, %r2, 8
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; CHECK: ic %r2, 0(%r3)
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; CHECK: br %r14
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%val = load i8 *%ptr
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%ptr2 = zext i8 %val to i64
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%ptr1 = shl i64 %orig, 8
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%or = or i64 %ptr1, %ptr2
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ret i64 %or
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}
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; Like f5, but with the operands reversed.
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define i64 @f6(i64 %orig, i8 *%ptr) {
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; CHECK-LABEL: f6:
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; CHECK: sllg %r2, %r2, 8
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; CHECK: ic %r2, 0(%r3)
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; CHECK: br %r14
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%val = load i8 *%ptr
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%ptr2 = zext i8 %val to i64
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%ptr1 = shl i64 %orig, 8
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%or = or i64 %ptr2, %ptr1
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ret i64 %or
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}
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; Check insertions into a constant.
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define i64 @f7(i64 %orig, i8 *%ptr) {
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; CHECK-LABEL: f7:
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; CHECK: lghi %r2, 256
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; CHECK: ic %r2, 0(%r3)
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; CHECK: br %r14
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%val = load i8 *%ptr
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%ptr2 = zext i8 %val to i64
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%or = or i64 %ptr2, 256
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ret i64 %or
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}
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; Like f7, but with the operands reversed.
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define i64 @f8(i64 %orig, i8 *%ptr) {
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; CHECK-LABEL: f8:
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; CHECK: lghi %r2, 256
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; CHECK: ic %r2, 0(%r3)
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; CHECK: br %r14
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%val = load i8 *%ptr
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%ptr2 = zext i8 %val to i64
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%or = or i64 256, %ptr2
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ret i64 %or
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}
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; Check the high end of the IC range.
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define i64 @f9(i64 %orig, i8 *%src) {
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; CHECK-LABEL: f9:
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; CHECK: ic %r2, 4095(%r3)
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; CHECK: br %r14
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%ptr = getelementptr i8 *%src, i64 4095
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%val = load i8 *%ptr
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%src2 = zext i8 %val to i64
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%src1 = and i64 %orig, -256
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%or = or i64 %src2, %src1
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ret i64 %or
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}
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; Check the next byte up, which should use ICY instead of IC.
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define i64 @f10(i64 %orig, i8 *%src) {
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; CHECK-LABEL: f10:
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; CHECK: icy %r2, 4096(%r3)
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; CHECK: br %r14
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%ptr = getelementptr i8 *%src, i64 4096
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%val = load i8 *%ptr
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%src2 = zext i8 %val to i64
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%src1 = and i64 %orig, -256
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%or = or i64 %src2, %src1
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ret i64 %or
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}
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; Check the high end of the ICY range.
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define i64 @f11(i64 %orig, i8 *%src) {
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; CHECK-LABEL: f11:
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; CHECK: icy %r2, 524287(%r3)
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; CHECK: br %r14
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%ptr = getelementptr i8 *%src, i64 524287
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%val = load i8 *%ptr
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%src2 = zext i8 %val to i64
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%src1 = and i64 %orig, -256
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%or = or i64 %src2, %src1
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ret i64 %or
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}
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; Check the next byte up, which needs separate address logic.
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; Other sequences besides this one would be OK.
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define i64 @f12(i64 %orig, i8 *%src) {
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; CHECK-LABEL: f12:
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; CHECK: agfi %r3, 524288
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; CHECK: ic %r2, 0(%r3)
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; CHECK: br %r14
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%ptr = getelementptr i8 *%src, i64 524288
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%val = load i8 *%ptr
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%src2 = zext i8 %val to i64
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%src1 = and i64 %orig, -256
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%or = or i64 %src2, %src1
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ret i64 %or
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}
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; Check the high end of the negative ICY range.
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define i64 @f13(i64 %orig, i8 *%src) {
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; CHECK-LABEL: f13:
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; CHECK: icy %r2, -1(%r3)
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; CHECK: br %r14
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%ptr = getelementptr i8 *%src, i64 -1
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%val = load i8 *%ptr
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%src2 = zext i8 %val to i64
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%src1 = and i64 %orig, -256
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%or = or i64 %src2, %src1
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ret i64 %or
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}
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; Check the low end of the ICY range.
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define i64 @f14(i64 %orig, i8 *%src) {
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; CHECK-LABEL: f14:
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; CHECK: icy %r2, -524288(%r3)
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; CHECK: br %r14
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%ptr = getelementptr i8 *%src, i64 -524288
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%val = load i8 *%ptr
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%src2 = zext i8 %val to i64
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%src1 = and i64 %orig, -256
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%or = or i64 %src2, %src1
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ret i64 %or
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}
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; Check the next byte down, which needs separate address logic.
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; Other sequences besides this one would be OK.
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define i64 @f15(i64 %orig, i8 *%src) {
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; CHECK-LABEL: f15:
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; CHECK: agfi %r3, -524289
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; CHECK: ic %r2, 0(%r3)
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; CHECK: br %r14
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%ptr = getelementptr i8 *%src, i64 -524289
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%val = load i8 *%ptr
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%src2 = zext i8 %val to i64
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%src1 = and i64 %orig, -256
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%or = or i64 %src2, %src1
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ret i64 %or
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}
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; Check that IC allows an index.
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define i64 @f16(i64 %orig, i8 *%src, i64 %index) {
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; CHECK-LABEL: f16:
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; CHECK: ic %r2, 4095({{%r4,%r3|%r3,%r4}})
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; CHECK: br %r14
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%ptr1 = getelementptr i8 *%src, i64 %index
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%ptr2 = getelementptr i8 *%ptr1, i64 4095
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%val = load i8 *%ptr2
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%src2 = zext i8 %val to i64
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%src1 = and i64 %orig, -256
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%or = or i64 %src2, %src1
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ret i64 %or
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}
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; Check that ICY allows an index.
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define i64 @f17(i64 %orig, i8 *%src, i64 %index) {
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; CHECK-LABEL: f17:
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; CHECK: icy %r2, 4096({{%r4,%r3|%r3,%r4}})
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; CHECK: br %r14
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%ptr1 = getelementptr i8 *%src, i64 %index
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%ptr2 = getelementptr i8 *%ptr1, i64 4096
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%val = load i8 *%ptr2
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%src2 = zext i8 %val to i64
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%src1 = and i64 %orig, -256
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%or = or i64 %src2, %src1
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ret i64 %or
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}
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