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db3c93e416
This will remove suboptimal branching from the generated ll/sc loops. The extra simplification pass affects a lot of testcases, which have been modified to accommodate this change: either by modifying the test to become immune to the CFG simplification, or (less preferablt) by adding option -hexagon-initial-cfg-clenaup=0. llvm-svn: 338774
65 lines
1.8 KiB
LLVM
65 lines
1.8 KiB
LLVM
; RUN: llc -march=hexagon -hexagon-initial-cfg-cleanup=0 < %s | FileCheck %s
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; REQUIRES: asserts
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; This used to crash. Check for some sane output.
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; CHECK: sath
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target triple = "hexagon"
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define void @fred() local_unnamed_addr #0 {
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b0:
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%v1 = load i32, i32* undef, align 4
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%v2 = tail call i32 @llvm.hexagon.A2.sath(i32 undef)
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%v3 = and i32 %v1, 603979776
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%v4 = trunc i32 %v3 to i30
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switch i30 %v4, label %b22 [
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i30 -536870912, label %b5
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i30 -469762048, label %b6
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]
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b5: ; preds = %b0
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unreachable
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b6: ; preds = %b0
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%v7 = load i32, i32* undef, align 4
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%v8 = sub nsw i32 65536, %v7
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%v9 = load i32, i32* undef, align 4
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%v10 = mul nsw i32 %v9, %v9
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%v11 = zext i32 %v10 to i64
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%v12 = mul nsw i32 %v2, %v8
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%v13 = sext i32 %v12 to i64
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%v14 = mul nsw i64 %v13, %v11
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%v15 = trunc i64 %v14 to i32
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%v16 = and i32 %v15, 2147483647
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store i32 %v16, i32* undef, align 4
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%v17 = lshr i64 %v14, 31
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%v18 = trunc i64 %v17 to i32
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store i32 %v18, i32* undef, align 4
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br label %b19
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b19: ; preds = %b6
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br i1 undef, label %b20, label %b21
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b20: ; preds = %b19
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unreachable
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b21: ; preds = %b19
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br label %b23
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b22: ; preds = %b0
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unreachable
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b23: ; preds = %b21
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%v24 = load i32, i32* undef, align 4
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%v25 = shl i32 %v24, 1
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%v26 = and i32 %v25, 65534
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%v27 = or i32 %v26, 0
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store i32 %v27, i32* undef, align 4
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ret void
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}
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declare i32 @llvm.hexagon.A2.sath(i32) #1
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attributes #0 = { nounwind "target-cpu"="hexagonv5" "target-features"="-hvx,-long-calls" }
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attributes #1 = { nounwind readnone }
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