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d4c615be8c
Discussed here: http://lists.llvm.org/pipermail/llvm-dev/2018-January/120320.html In preparation for adding support for named vregs we are changing the sigil for physical registers in MIR to '$' from '%'. This will prevent name clashes of named physical register with named vregs. llvm-svn: 323922
27 lines
713 B
YAML
27 lines
713 B
YAML
# RUN: llc -march=hexagon -mattr=+hvx,+hvx-length64b -run-pass hexagon-vextract %s -o - | FileCheck %s
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---
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name: fred
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $r0, $r1, $v0
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%0:hvxvr = COPY $v0
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%1:intregs = COPY $r0
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%2:intregs = COPY $r1
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%3:intregs = A2_tfrsi 5
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%4:intregs = V6_extractw %0, %1
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; CHECK: %[[A0:[0-9]+]]:intregs = A2_andir %{{[0-9]+}}, -4
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; CHECK: L4_loadri_rr %{{[0-9]+}}, %[[A0]], 0
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%5:intregs = V6_extractw %0, %2
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; CHECK: %[[A1:[0-9]+]]:intregs = A2_andir %{{[0-9]+}}, -4
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; CHECK: L4_loadri_rr %{{[0-9]+}}, %[[A1]], 0
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%6:intregs = V6_extractw %0, %3
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; Make sure the offset is 4, not 5.
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; CHECK: L2_loadri_io %{{[0-9]+}}, 4
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...
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