1
0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-11-23 03:02:36 +01:00
llvm-mirror/docs/AMDGPU/gfx10_vcc_32.rst
Dmitry Preobrazhensky 50947152c2 [AMDGPU][MC][NFC][DOC] Updated AMD GPU assembler syntax description.
Summary of changes:
- added description of MTBUF instructions and format modifier;
- described limitations of f16 inline constants when used with integer operands;
- updated description of gfx9+ flat global addressing modes;
- v_accvgpr_write_b32 src0 corrections (gfx908);
- minor bugfixing and improvements.
2020-08-21 14:25:14 +03:00

17 lines
542 B
ReStructuredText

..
**************************************************
* *
* Automatically generated file, do not edit! *
* *
**************************************************
.. _amdgpu_synid10_vcc_32:
vcc
===========================
Vector condition code. This operand depends on wavefront size:
* Should be :ref:`vcc_lo<amdgpu_synid_vcc_lo>` if wavefront size is 32.
* Should be :ref:`vcc<amdgpu_synid_vcc>` if wavefront size is 64.